Статьи на перевод PVDF_P(VDF-TrFE) / Память на с-э полимерах

Ferroelectric-gate field-effect transistors (Fe-FETs) employing ferroelectric layers as gate insulators have received attention due to their benefits, including a non-destructive readout capability, scalable feature size of 4F2, and low operating voltages.[1,2] In an Fe-FET, the polarization state of the ferroelectric layer is set by the polarity of the program/erase gate voltage, which controls accumulation or depletion of carriers in the semiconducting channel between the source and drain electrode.[2,3] Due to the potential advantages of ferroelectric polymers including their low cost, easy solution processes fabrication, and mechanical pliability (which allows for the production of flexible, foldable, and stretchable devices), great efforts have been devoted to improve the properties of Fe-FETs using ferroelectric polymers such as poly(vinylidene fluoride) (PVDF) and its copolymers with trifluoroethylene (PVDF-TrFE). In particular, efforts have been made to improve their non-destructive readout capa- bility,[3,4–6] flexibility,[6,7] printing capability,[8] endurance,[3,9] long data retention,[3,4,6] short program pulse width,[3] large ON/OFF ratio,[3,4,8,9] and operating voltage,[10] as well as material design including electrodes,[3] ferroelectric and insulating layers,[4,6,10] and organic semiconducting active layers.[3,4–6,8,11–21]

One of the most pressing issues yet to be significantly addressed is the fabrication of high-density Fe-FETs. Highdensity memories can be realized by continuous scale-down of individual cell dimensions as well as 3D stacking of planar arrays of memory elements.[22] However, these two approaches require elaborate and expensive micro/nanofabrication processes which are often harmful to polymers, as well as very careful selection of materials appropriate for the multistacking solution process. An alternative solution is a memory cell with multilevel data storage capability.

A variety of multilevel memory cells (MLCs) have recently been fabricated based on either flash or resistive switching operation.[23–28] The key materials of the majority of MLCs are inorganic, such as Au nanoparticles,[23] Ni nanocrystals,[24] and ZrO2[25] and cobalt oxide nanowires.[26] Only a few organic MLCs have been fabricated, and these made use of small molecules[27] and solution-processed graphene oxide.[28] Multilevel operation of memory cells containing mechanically stiff inorganic

S. K. Hwang, I. Bae, R. H. Kim, Prof. C. Park,

Department of Materials Science and Engineering

Yonsei University

Seoul, 120-749, Republic of Korea

E-mail: cmpark@yonsei.ac.kr

DOI: 10.1002/adma.201201831

semiconducting channels was also achieved using ferroelectrics under principles of continuous ferroelectric domain switching of PbZrT1–xO3 (PZT), as well as periodic thickness variation of a PVDF-TrFE layer by nanoimprinting lithography.[29,30] However, they frequently suffer from poor data reliability, and in particular, unstable switching endurance.

In this paper, we demonstrate a highly reliable and mechanically flexible MLC Fe-FET with a thin PVDF-TrFE insulator. Our device is based on multileveled non-volatile drain current states of a polymeric semiconductor precisely controlled by a ferroelectric insulator. Various remnant polarization states which arise from distributed domain polarization of the ferroelectric layer as a function of the applied gate voltage in turn dictate the interstate levels of the source-drain current (IDS), giving rise to a highly reliable 4-level MLC Fe-FET. Each level of the device exhibited excellent data retention and endurance of more than 105 s and 102 cycles, respectively. Furthermore, our gate-controlled multilevel Fe-FETs with poly(3-hexyl thiophene) (P3HT) active channels are mechanically flexible with characteristic multilevels even after more than 1000 bending cycles, with a bending radius of 5.8 mm.

An Fe-FET memory device with a top-gate bottom-contact (TGBC) structure consisting of an Au source-drain (S/D) elec- trode/P3HT/PVDF-TrFE/Al gate electrode was constructed on either a Si wafer or a flexible polymer substrate as schematically illustrated in Figure 1a. The TGBC structure is suitable for high-density circuit design and is also effective for facile accumulation of charge carriers in channels upon non-volatile dipole switching of PVDF-TrFE by a gate voltage (VG).[31] A 100 nm-thick P3HT layer was directly spin-coated from solution in 1, 2-dichlorobenzene onto the patterned Au S/D electrodes. Subsequently, a 700 nm-thick PVDF-TrFE layer (60 mg/ml in methyl ethyl ketone (MEK) solvent) was spin-coated onto the P3HT layer, followed by thermal evaporation of the Al gate electrodes. To isolate between two cells as well as to make the Au S/D electrode accessible to contact probes, both the P3HT and PVDF-TrFE layers in the regions outside the areas covered by the top Al electrodes were etched by oxygen plasma using reactive ion etching (RIE), producing an Fe-FET device. The Fe-FET device was visualized using scanning electron microscopy (SEM) and optical microscopy, as shown in Figure 1a.

The Fe-FET with the P3HT channel layer exhibited p-type output characteristics in the IDS versus source-drain voltage (VDS) curve and the transfer curve (at a VDS of –5 V), which showed current hysteresis as a function of VG arising from the ferroelectric polarization switching of PVDF-TrFE, as shown in Figure 1b,c. The hysteresis curve was saturated when a VG above ±80 V was applied. After the device was turned on, there was a rapid increase of the IDS with a negative bias in VG due

Figure 4. The multilevel IDS values of a flexible Fe-FET memory: a) as a function of the bending radius, and b) as a function of the number of bending cycles under a bending radius of 5.8 mm. The inset in (a) exhibits a photograph of a flexible Fe-FET obtained under bending. The photographs in the inset of (b) show arrays of Fe-FETs in bent and unbent states.

cycles.[23,24,27] Our Fe-FET memory is beneficial because of the non-destructive device operation with FET architecture based on polarization switching, which is electrically much more stable than conduction switching. As a result, our multilevel FeFETs demonstrated good cell-to-cell uniformity in the IDS distribution at each level (Supporting information, S3).

Flexible multilevel Fe-FETs fabricated on polyimide substrates also showed reliable four-level non-volatile I–V characteristics similar to those on SiO2 (Supporting information, S4). We investigated the bending stability of our device in which four independent IDS values set up with corresponding gate voltage sweeps were monitored as a function of the bending radius, as shown in Figure 4a. The IDS values of the four states were similar, without any notable current fluctuation even under a bending radius of 5.8 mm, as shown in Figure 4a (Supporting information, S4). We further examined the memory stability of our Fe-FET as a function of the number of bending cycles. The

device exhibited very stable four-level memory characteristics after more than 1000 bending cycles using a radius of 5.8 mm, as shown in Figure 4b. Our four-level Fe-FET on a flexible substrate also demonstrated reliable long term data retention and multiple write/erase endurance under severe bending at a radius of 5.8 mm (Supporting information, S5). Considering that Curie temperature of the PVDF-TrFE is approximately 80 °C, our results clearly suggest that 1 T memory based on ferroelectric polymer can be one of the most-promising candidates for emerging flexible, high-density, non-volatile memories with reasonable thermal margin.

In summary, we have demonstrated a flexible non-volatile Fe-FET memory with multilevel switching behavior by precisely controlling the degree of remnant polarization of a ferroelectric PVDF-TrFE gate insulator which was dependent on the applied gate voltage. Four levels of discrete non-volatile source-drain currents were readily achieved with the application of an appropriate programming/reading gate voltage, and the memory exhibited an excellent data retention of more than 105 s and a notable multiple write/erase endurance of 102 cycles. Furthermore, our multilevel Fe-FET fabricated on a polymer substrate provided mechanical flexibility in which the characteristic 4-level reliable switching was also realized with more than 1000 bending cycles at a bending radius of 5.8 mm. Our results offer a novel design strategy for low-cost high-density organic memory and are conveniently adoptable for various flexible and foldable organic electronic devices.

Experimental Section

Materials and Film Preparation: PVDF-TrFE with 25 wt% TrFE was purchased from MSI Sensors. P3HT (Mw = 180 000 g mol−1 with 98.5% head-to-tail regioregularity) was purchased from Sigma–Aldrich, Korea. All of the organic solvents including methyl ethyl ketone (MEK) and 1,2-dichlorobenzne (DCB) were purchased from Sigma–Aldrich, Korea. A P3HT solution in DCB (1 wt%) was spin-coated at 2000 rpm for 70 s on either a SiO2 (500 nm) or polyimide substrate with patterned Au S/D electrodes. A PVDF-TrFE solution in MEK (40, 60, and 80 mg/ml) was spin-coated at 1500 rpm for 60 s on a P3HT layer. The spin-coated films were dried under vacuum for 2 h at 60 °C.

Device Fabrication and Characterization: SiO2 substrates were cleaned in an ultrasonic bath with acetone and ethanol for 1 h each while the polyimide substrates used to make the flexible device were cleaned only in ethanol for 2 h. Firstly, arrays of 30 nm-thick Au S/D electrodes were thermally evaporated on a substrate with a patterned shadow mask under a vacuum of 10−6 Torr (SNTEK MEP5000). Subsequently, an approximately 100 nm-thick P3HT layer was spin-coated, followed by thin-film formation of a ferroelectric PVDF-TrFE insulator. The PVDFTrFE solution in MEK did not affect the underlying P3HT layer. After thermal treatment at 60 °C for 1 h to remove the residual solvents in both the P3HT and PVDF-TrFE layers, 60 nm-thick top gate Al electrodes were deposited by thermal evaporation under a vacuum of 10−6 Torr with a patterned shadow mask aligned with respect to the S/D electrodes previously formed. In order to make the Au S/D electrode accessible with contact probe tips, the devices were further treated with oxygen plasma (100 W for 200 s, 10−3 Torr, 40 sccm) generated by reactive ion etching (RIE) (Femto VITA-4E). Arrays of Al gate electrodes were used as RIE blocking masks, giving rise to top-gate-bottom-contact Fe-FET memories with S/D electrodes open to the air, as illustrated in the schematic in Figure 1a. The electrical characteristics were measured by semiconductor systems (E5270B, Agilent Technologies) under ambient conditions. Fieldemission scanning electron microscope (FESEM) images were obtained