Recommended serial interface for transceiver control V1.0a
.pdf
Serial Interface for Transceiver Control
RESET
SH[7:0] |
CONTROL REG 5 |
|
INDX[3] |
|
D[7:0] |
Q[7:0] |
INDX[2] |
|
CK |
|
INDX[1] |
|
ALD |
|
INDX[0] |
|
|
|
|
REGC8 |
||
|
|
||
|
|
CONTROL REG 4 |
|
INDX[3] |
WAL# |
D[7:0] |
Q[7:0] |
INDX[2] |
CK |
|
|
|
|
||
INDX[1] |
|
ALD |
|
INDX[0] |
|
|
|
|
REGC8 |
||
|
|
||
|
|
CONTROL REG 3 |
|
INDX[3] |
WPR# |
D[7:0] |
Q[7:0] |
INDX[2] |
CK |
|
|
|
|
||
INDX[1] |
|
ALD |
|
INDX[0] |
|
|
|
|
REGC8 |
||
|
|
||
|
|
CONTROL REG 2 |
|
INDX[3] |
|
D[7:0] |
Q[7:0] |
INDX[2] |
|
CK |
|
INDX[1] |
|
ALD |
|
INDX[0] |
|
|
|
|
REGC8 |
||
|
|
||
|
|
CONTROL REG 1 |
|
INDX[3] |
|
D[7:0] |
Q[7:0] |
INDX[2] |
|
CK |
|
INDX[1] |
|
ALD |
|
INDX[0] |
|
|
|
|
REGC8 |
||
|
|
||
|
|
CONTROL REG 0 |
|
INDX[3] |
|
D{7:0] |
Q[7:0] |
INDX[2] |
|
CK |
|
INDX[1] |
|
ALD |
|
INDX[0] |
|
|
|
|
REGC8 |
||
|
|
||
WTR2 |
|
|
|
WR_EN |
|
|
|
ESC |
|
8-BIT 2-TO-1 MUX |
|
|
CTL3[7:0] |
A[7:0] |
|
CTL4[7:0] |
|
B[7:0] Z[7:0] |
|
SL
WAL#
MX2W4
WPR#
AGC_RST
CTL5[7:0]
(RX CHANNEL BANDWIDTH)
CTL4[7:0]
(ALT. SENSITIVITY)
CTL3[7:0]
(PRIMARY SENSITIVITY)
CTL2[7:0] (TX POWER LEVEL)
CTL1[7:0] (MODE SELECTION)
CTL0[7:0] (PM_SL, RX_OEN, TLED_EN, DM_EN, APEN, AGCMSK, TAUX_EN)
TRSH[7:0]
NOTE: ASSERTION OF ALD (ASYNCH. LOAD) CAUSES THE REGISTERS TO BE LOADED WITH THE DEFAULT VALUES
Figure A-2. Transceiver Control Registers
21
Serial Interface for Transceiver Control
|
|
|
|
|
|
0 |
DAT/ |
|
|
|
|
|
|
DAT |
|
|
|
|
|
|
|
1 |
|
13 |
|
|
|
|
|
CLD |
|
RES |
|
15 |
|
14 |
|
SHF |
|
|
|
|
IST00 |
|
|||
|
RES |
|
RES |
|
|
||
|
|
|
|
|
|
||
|
|
IST00 |
|
IST01 |
|
|
|
|
|
|
|
DAT/ & |
2 |
CNT6/ |
|
|
|
|
|
AR |
|
SHF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IST00 |
|
DAT/ |
|
|
DAT/ & RS |
|
CNT6 |
||
|
12 |
|
|
|
|
||
|
|
|
|
|
3 |
|
|
RX_DIS |
|
DAT/ & SPC & AR/ & RS/ |
|
|
|||
|
|
|
|
||||
|
|
|
|
WTR1 |
|
||
|
|
|
|
|
|
|
|
|
|
|
DAT/ & SPC/ |
|
|
|
|
DAT/ |
|
& SLA/ |
|
DAT/ & |
DAT |
|
|
|
|
|
|
||||
|
11 |
|
|
7 |
SPC/ & |
|
|
|
|
|
SLA |
|
|
||
|
RX_DIS |
|
|
RX_DIS |
4 |
|
|
DAT |
|
|
|
|
|||
IST00 |
|
|
IST01 |
|
CLD |
|
|
|
|
8 |
|
|
|||
|
|
|
|
|
|
||
|
|
|
|
|
SHF |
|
|
|
|
|
RX_DIS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RX_EN |
|
|
|
|
DAT/ |
|
|
DAT |
5 |
CNT6/ |
||
|
|
|
|
|
|
||
|
10 |
|
9 |
DAT/ & |
|
SHF |
|
|
|
|
|
|
|||
|
RX_DIS |
RX_DIS |
|
|
|
||
DAT |
RD_EN |
|
|
|
|||
RX_EN |
|
RX_EN |
|
|
CNT6 |
||
|
|
|
|
||||
|
SHF |
|
SPLD |
|
|
||
|
|
|
|
6 |
|
||
|
|
|
|
|
|
|
|
|
|
|
DAT/ & WR/ & RD_EN/ |
|
WTR2 |
|
|
|
|
|
|
DAT/ & WR |
|
|
|
Figure A-3. Serial Interface State Diagram, (Slave Side)
22
Serial Interface for Transceiver Control
APPENDIX B
Interconnecting two transceivers with the same address.
The following configuration allows two transceivers having the same fixed address to be used in a system.
This configuration is not part of this specification and should only be considered as an interim solution since it is not expandable and does not support Plug-n-Play.
It is strongly recommended that future transceivers provide support for at least two selectable addresses.
|
|
OFE A |
|
|
|
IRTX/SWDAT |
TX/SWDAT |
|
|
|
IRRX/SRDAT |
|
||
Infrared |
RX/SRDAT |
Optical |
||
SCLK1 |
|
Transceiver |
||
Controller |
SCLK |
|||
SCLK2 |
|
|||
|
|
|
VCC
OFE B
TX/SWDAT |
|
|
RX/SRDAT |
Optical |
|
Transceiver |
||
SCLK |
||
|
Figure B-1. Interface to Two Infrared Transceivers.
The data lines are multiplexed with the transmitter and receiver signals and separate clocks are used since the transceivers respond to
the same address.
23