FreeBSD developers' handbook.2001
.pdfChapter 10 DMA
0xca |
write |
Channel 6 starting word count |
0xca |
read |
Channel 6 remaining word count |
0xcc |
write |
Channel 7 starting address |
0xcc |
read |
Channel 7 current address |
0xce |
write |
Channel 7 starting word count |
0xce |
read |
Channel 7 remaining word count |
DMA Command Registers |
|
|
0xd0 |
write |
Command Register |
0xd0 |
read |
Status Register |
0xd2 |
write |
Request Register |
0xd2 |
read |
- |
0xd4 |
write |
Single Mask Register Bit |
0xd4 |
read |
- |
0xd6 |
write |
Mode Register |
0xd6 |
read |
- |
0xd8 |
write |
Clear LSB/MSB Flip-Flop |
0xd8 |
read |
- |
0xda |
write |
Master Clear/Reset |
0xda |
read |
Temporary Register (not present in |
|
|
Intel 82374) |
0xdc |
write |
Clear Mask Register |
0xdc |
read |
- |
0xde |
write |
Write All Mask Register Bits |
0xdf |
read |
Read All Mask Register Bits (only in |
|
|
Intel 82374) |
10.1.5.3 0x80–0x9f DMA Page Registers
0x87 |
r/w |
Channel 0 Low byte (23-16) page |
|
|
Register |
0x83 |
r/w |
Channel 1 Low byte (23-16) page |
|
|
Register |
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Chapter 10 DMA
0x81 |
r/w |
Channel 2 Low byte (23-16) page |
|
|
Register |
0x82 |
r/w |
Channel 3 Low byte (23-16) page |
|
|
Register |
0x8b |
r/w |
Channel 5 Low byte (23-16) page |
|
|
Register |
0x89 |
r/w |
Channel 6 Low byte (23-16) page |
|
|
Register |
0x8a |
r/w |
Channel 7 Low byte (23-16) page |
|
|
Register |
0x8f |
r/w |
Low byte page Refresh |
10.1.5.4 0x400–0x4ff 82374 Enhanced DMA Registers
The Intel 82374 EISA System Component (ESC) was introduced in early 1996 and includes a DMA controller that provides a superset of 8237 functionality as well as other PC-compatible core peripheral components in a single package. This chip is targeted at both EISA and PCI platforms, and provides modern DMA features like scatter-gather, ring buffers as well as direct access by the system DMA to all 32 bits of address space.
If these features are used, code should also be included to provide similar functionality in the previous 16 years worth of PC-compatible computers. For compatibility reasons, some of the 82374 registers must be programmed after programming the traditional 8237 registers for each transfer. Writing to a traditional 8237 register forces the contents of some of the 82374 enhanced registers to zero to provide backward software compatibility.
0x401 |
r/w |
Channel 0 High byte (bits 23-16) word |
|
|
count |
0x403 |
r/w |
Channel 1 High byte (bits 23-16) word |
|
|
count |
0x405 |
r/w |
Channel 2 High byte (bits 23-16) word |
|
|
count |
0x407 |
r/w |
Channel 3 High byte (bits 23-16) word |
|
|
count |
0x4c6 |
r/w |
Channel 5 High byte (bits 23-16) word |
|
|
count |
0x4ca |
r/w |
Channel 6 High byte (bits 23-16) word |
|
|
count |
63
Chapter 10 DMA
0x4ce |
r/w |
Channel 7 High byte (bits 23-16) word |
|
|
count |
0x487 |
r/w |
Channel 0 High byte (bits 31-24) page |
|
|
Register |
0x483 |
r/w |
Channel 1 High byte (bits 31-24) page |
|
|
Register |
0x481 |
r/w |
Channel 2 High byte (bits 31-24) page |
|
|
Register |
0x482 |
r/w |
Channel 3 High byte (bits 31-24) page |
|
|
Register |
0x48b |
r/w |
Channel 5 High byte (bits 31-24) page |
|
|
Register |
0x489 |
r/w |
Channel 6 High byte (bits 31-24) page |
|
|
Register |
0x48a |
r/w |
Channel 6 High byte (bits 31-24) page |
|
|
Register |
0x48f |
r/w |
High byte page Refresh |
0x4e0 |
r/w |
Channel 0 Stop Register (bits 7-2) |
0x4e1 |
r/w |
Channel 0 Stop Register (bits 15-8) |
0x4e2 |
r/w |
Channel 0 Stop Register (bits 23-16) |
0x4e4 |
r/w |
Channel 1 Stop Register (bits 7-2) |
0x4e5 |
r/w |
Channel 1 Stop Register (bits 15-8) |
0x4e6 |
r/w |
Channel 1 Stop Register (bits 23-16) |
0x4e8 |
r/w |
Channel 2 Stop Register (bits 7-2) |
0x4e9 |
r/w |
Channel 2 Stop Register (bits 15-8) |
0x4ea |
r/w |
Channel 2 Stop Register (bits 23-16) |
0x4ec |
r/w |
Channel 3 Stop Register (bits 7-2) |
0x4ed |
r/w |
Channel 3 Stop Register (bits 15-8) |
0x4ee |
r/w |
Channel 3 Stop Register (bits 23-16) |
0x4f4 |
r/w |
Channel 5 Stop Register (bits 7-2) |
0x4f5 |
r/w |
Channel 5 Stop Register (bits 15-8) |
0x4f6 |
r/w |
Channel 5 Stop Register (bits 23-16) |
0x4f8 |
r/w |
Channel 6 Stop Register (bits 7-2) |
0x4f9 |
r/w |
Channel 6 Stop Register (bits 15-8) |
0x4fa |
r/w |
Channel 6 Stop Register (bits 23-16) |
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Chapter 10 DMA
0x4fc |
r/w |
Channel 7 Stop Register (bits 7-2) |
0x4fd |
r/w |
Channel 7 Stop Register (bits 15-8) |
0x4fe |
r/w |
Channel 7 Stop Register (bits 23-16) |
0x40a |
write |
Channels 0-3 Chaining Mode Register |
0x40a |
read |
Channel Interrupt Status Register |
0x4d4 |
write |
Channels 4-7 Chaining Mode Register |
0x4d4 |
read |
Chaining Mode Status |
0x40c |
read |
Chain Buffer Expiration Control |
|
|
Register |
0x410 |
write |
Channel 0 Scatter-Gather Command |
|
|
Register |
0x411 |
write |
Channel 1 Scatter-Gather Command |
|
|
Register |
0x412 |
write |
Channel 2 Scatter-Gather Command |
|
|
Register |
0x413 |
write |
Channel 3 Scatter-Gather Command |
|
|
Register |
0x415 |
write |
Channel 5 Scatter-Gather Command |
|
|
Register |
0x416 |
write |
Channel 6 Scatter-Gather Command |
|
|
Register |
0x417 |
write |
Channel 7 Scatter-Gather Command |
|
|
Register |
0x418 |
read |
Channel 0 Scatter-Gather Status |
|
|
Register |
0x419 |
read |
Channel 1 Scatter-Gather Status |
|
|
Register |
0x41a |
read |
Channel 2 Scatter-Gather Status |
|
|
Register |
0x41b |
read |
Channel 3 Scatter-Gather Status |
|
|
Register |
0x41d |
read |
Channel 5 Scatter-Gather Status |
|
|
Register |
0x41e |
read |
Channel 5 Scatter-Gather Status |
|
|
Register |
65
Chapter 10 DMA
0x41f |
read |
Channel 7 Scatter-Gather Status |
|
|
Register |
0x420-0x423 |
r/w |
Channel 0 Scatter-Gather Descriptor |
|
|
Table Pointer Register |
0x424-0x427 |
r/w |
Channel 1 Scatter-Gather Descriptor |
|
|
Table Pointer Register |
0x428-0x42b |
r/w |
Channel 2 Scatter-Gather Descriptor |
|
|
Table Pointer Register |
0x42c-0x42f |
r/w |
Channel 3 Scatter-Gather Descriptor |
|
|
Table Pointer Register |
0x434-0x437 |
r/w |
Channel 5 Scatter-Gather Descriptor |
|
|
Table Pointer Register |
0x438-0x43b |
r/w |
Channel 6 Scatter-Gather Descriptor |
|
|
Table Pointer Register |
0x43c-0x43f |
r/w |
Channel 7 Scatter-Gather Descriptor |
|
|
Table Pointer Register |
66
V. I/O System
Chapter 11 UFS
UFS, FFS, Ext2FS, JFS, inodes, buffer cache, labeling, locking, metadata, soft-updates, LFS, portalfs, procfs, vnodes, memory sharing, memory objects, TLBs, caching
68
VI. Interprocess Communication
Chapter 12 Signals
Signals, pipes, semaphores, message queues, shared memory, ports, sockets, doors
70
VII. Networking