21 List of instruction timings for P1 and PMMX

21.1 Integer instructions (P1 and PMMX)

Explanation of column headings:

Operands: r = register, m = memory, i = immediate data, sr = segment register m32 = 32 bit memory operand, etc.

Clock cycles: The numbers are minimum values. Cache misses, misalignment, and exceptions may increase the clock counts considerably.

Pairability: u = pairable in u-pipe, v = pairable in v-pipe, uv = pairable in either pipe, np = not pairable.

Notes:

a)this instruction has a 0FH prefix which takes one clock cycle extra to decode on a P1 unless preceded by a multicycle instruction (see page 57).

b)versions with FS and GS have a 0FH prefix. see note a.

c)versions with SS, FS, and GS have a 0FH prefix. see note a.

d)versions with two operands and no immediate have a 0FH prefix, see note a.

e)see page 40 (P1) and 43 (PMMX).

f)only pairable if register is AL, AX or EAX.

g)add one clock cycle for decoding the repeat prefix unless preceded by a multicycle instruction (such as CLD).

h)pairs as if it were writing to the accumulator.

i)9 if SP divisible by 4. See page 54.

j)on P1: 6 in privileged or real mode; 11 in nonprivileged; error in virtual mode. On PMMX: 8 and 13 clocks respectively.

21.2 Floating-point instructions (P1 and PMMX)

Explanation of column headings:

Operands: r = register, m = memory, m32 = 32 bit memory operand, etc.

Clock cycles: The numbers are minimum values. Cache misses, misalignment, denormal operands, and exceptions may increase the clock counts considerably.

Pairability: + = pairable with FXCH, np = not pairable with FXCH.

i-ov: Overlap with integer instructions. i-ov = 4 means that the last four clock cycles can overlap with subsequent integer instructions.

fp-ov: Overlap with floating-point instructions. fp-ov = 2 means that the last two clock cycles can overlap with subsequent floating-point instructions. (WAIT is considered a floating-point instruction here)

Notes:

m)The value to store is needed one clock cycle in advance.

n)1 if the overlapping instruction is also an FMUL.

o)Cannot overlap integer multiplication instructions.

p)FDIV takes 19, 33, or 39 clock cycles for 24, 53, and 64 bit precision respectively. FIDIV takes 3 clocks more. The precision is defined by bit 8-9 of the floating-point control word.

q)The first 4 clock cycles can overlap with preceding integer instructions. See page 122.

r)clock counts are typical. Trivial cases may be faster, extreme cases may be slower.

s)may be up to 3 clocks more when output needed for FST, FCHS, or FABS.