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Санкт-Петербургский государственный электротехнический университет "ЛЭТИ"

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Электротехника

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Dueck R.Digital design with CPLD applications and VHDL.2000

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788 Answers to Selected Odd-Numbered Problems

INPUT

NOT

AND3

VCC

AND3

AND6

AND2

AND3

AND4

AND6

OUTPUT Q3

OR4

OUTPUT Q2

OR4

OUTPUT Q1

OR6

OUTPUT Q0

GND

FIGURE ANS5.19A

Answers to Selected Odd-Numbered Problems

789

FIGURE ANS5.19B

FIGURE ANS5.21

790 Answers to Selected Odd-Numbered Problems

5.23See Figure ANS5.23

See page 787 for Truth Tables.

5.25Y S2S1S0D0 S2S1S0D1 S2S1S0D2 S2S1S0D3 S2S1S0D4 S2S1S0D5 S2S1S0D6 S2S1S0D7

FIGURE ANS5.23

S2 S1 S0

a. 8-to-1

1 0 1 D0 1 0 1 D1 1 0 1 D2

1 0 1 D3 1 0 1 D4 1 0 1 D5

1 0 1 D6 1 0 1 D7

0 D0 0 D1 0 D2 0 D3 D4 1 D5

0 D6 0 D7

D10

D11

D12

D13

D14

D15

S3 S2 S1 S0

b. 16-to-1

5.27—— quad8to1.vhd

——Eight-channel 4-bit multiplexer

——One of eight sets four inputs

——(d03..d00), (d13..d10), (d23..d20), (d33..d30),

——(d43..d40), (d53..d50), (d63..d60), (d73..d70)

——is directed to an output (y), based on the status of three

——select inputs (s2, s1, s0).

ENTITY quad8to1 IS

PORT(

s	: IN	INTEGER RANGE 0 to 7;
d0	: IN	BIT_VECTOR (3 downto 0);
d1	: IN	BIT_VECTOR (3 downto 0);
d2	: IN	BIT_VECTOR (3 downto 0);
d3	: IN	BIT_VECTOR (3 downto 0);
d4	: IN	BIT_VECTOR (3 downto 0);
d5	: IN	BIT_VECTOR (3 downto 0);
d6	: IN	BIT_VECTOR (3 downto 0);
d7	: IN	BIT_VECTOR (3 downto 0);
y	: OUT BIT_VECTOR (3 downto 0));

END quad8to1;

Answers to Selected Odd-Numbered Problems

791

ARCHITECTURE mux8 OF quad8to1 IS

BEGIN

—— Selected Signal Assignment

MUX4: WITH s SELECT
y <=	d0 WHEN 0,
	d1	WHEN 1,
	d2	WHEN 2,
	d3	WHEN 3,
	d4	WHEN 4,
	d5	WHEN 5,
	d6	WHEN 6,
	d7	WHEN 7;
END mux8;

FIGURE ANS5.27

The simulation of this circuit is shown in Figure ANS5.27.

5.29—— oct4to1.vhd

——Four-channel 8-bit multiplexer

——One of four sets eight inputs

——(d07..d00), (d17..d10), (d27..d20), or (d37..d30)

——is directed to a an output (y), based on the status of two

——select inputs (s1, s0).

ENTITY oct4to1 IS

PORT(

s	: IN	INTEGER RANGE 0 to 3;
d0	: IN	BIT_VECTOR (7 downto 0);
d1	: IN	BIT_VECTOR (7 downto 0);
d2	: IN	BIT_VECTOR (7 downto 0);
d3	: IN	BIT_VECTOR (7 downto 0);
y	: OUT BIT_VECTOR (7 downto 0));

792 Answers to Selected Odd-Numbered Problems

END oct4to1;

ARCHITECTURE mux4 OF oct4to1 IS

BEGIN

—— Selected Signal Assignment

MUX8: WITH s SELECT
y	<=	d0 WHEN 0,
		d1	WHEN 1,
		d2	WHEN 2,
		d3	WHEN 3;
END mux4;

FIGURE ANS5.29

The simulation is shown in Figure ANS5.29.

5.31ENTITY mux_8ch IS

PORT(
sel	: IN	BIT_VECTOR (2 downto 0);
d	: IN	BIT_VECTOR (7 downto 0);
y	: OUT BIT);
END mux_8ch;
ARCHITECTURE a OF mux_8ch IS
BEGIN
—— Selected Signal Assignment
MUX8: WITH sel SELECT
y	<=	d(0) WHEN “000”,
		d(1)	WHEN “001”,
		d(2)	WHEN “010”,
		d(3)	WHEN “011”,
		d(4)	WHEN “100”,
		d(5)	WHEN “101”,
		d(6)	WHEN “110”,
		d(7)	WHEN	An 8-to-1 MUX can be easily extended to a 16-bit device
“111”;				by adding one select input, eight data inputs, and eight
END a;

Answers to Selected Odd-Numbered Problems

793

INPUT

DATA

NOT

AND4

OUTPUT

AND4

OUTPUT

AND4

OUTPUT

AND4

OUTPUT

AND4

OUTPUT

AND4

OUTPUT

AND4

OUTPUT

AND4

OUTPUT

FIGURE ANS5.37A

794 Answers to Selected Odd-Numbered Problems

FIGURE ANS5.37B

lines to the selected signal assignment statement.

5.3500110011; 00001111

5.37See Figure ANS5.37.

		74HC4052

	X0
	X0
Transmit	X1
Transmit	X1
channels	X2	X
	X2	X
	X3		Telephone
	X3

			System
	Y0	Y
	Y0
Receive	Y1
Receive	Y1
channels	Y2
channels

	Y3	S1 S0
	Y3	S1 S0

Q1 Q0

CLOCK

CTR DIV 4

FIGURE ANS5.41

5.39An analog switch can transmit a range of positive and negative voltages, not just 0V and 5V.

5.41See Figure ANS5.41

5.43See Figure ANS5.43. The glitch in the simulation is caused by propagation delay.

5.45 AEQB (A B )(A B )(A B )(A B )

5 5 4 4 3 3 2 2

(A B )(A B )

1 1 0 0

AGTB A B A B (A B )

5 5 4 4 5 5

A B (A B )(A B )

3 3 5 5 4 4

A B (A B )(A B )(A B )

2 2 5 5 4 4 3 3

A B (A B )(A B )(A B )

1 1 5 5 4 4 3 3

(A B )

2 2

A B (A B )(A B )(A B )

0 0 5 5 4 4 3 3

(A B )(A B )

2 2 1 1

ALTB A B A B (A B ) A B

5 5 4 4 5 5 3 3

(A B )(A B )

5 5 4 4

A B (A B )(A B )(A B )

2 2 5 5 4 4 3 3

A B (A B )(A B )(A B )

1 1 5 5 4 4 3 3

INPUT

XNOR

NOT

Answers to Selected Odd-Numbered Problems

795

VCC

AND6

AND4 OR4

OUTPUT A_LT_B

AND3

AND2

FIGURE ANS5.43

(A B )

2 2

A B (A B )(A B )(A B )

0 0 5 5 4 4 3 3

(A B )(A B )

2 2 1 1

5.47—— cmp4x6.vhd

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY cmp4x6 IS PORT(

796	Answers to Selected Odd-Numbered Problems
	a, b : IN INTEGER RANGE 0 TO 15;
	altb, aleb, aeqb, aneb, ageb, agtb : OUT STD_LOGIC);
	END cmp4x6;
	ARCHITECTURE a OF cmp4x6 IS
	SIGNAL compare	: STD_LOGIC_VECTOR (5 downto 0);
	BEGIN
	PROCESS (a,b)
	BEGIN

IF a<b THEN
	compare		<=	“001011”;
ELSIF	a=b THEN
	compare		<=	“100101”;
ELSIF	a>b THEN
	compare		<=	“111000”;
ELSE
	compare		<=	“111111”;
END IF;
altb	<=	compare (5); —— a is less than b
aleb	<=	compare (4); —— a is less than or equal to b
aeqb	<=	compare (3); —— a equals b
aneb	<=	compare (2); —— a is not equal to b

ageb	<=	compare	(1); —
— a is greater than or equal to			b
agtb	<=	compare	(0); —
— a is greater than b
END PROCESS;
END a;

b.1010110; four 1s; PE 0; PO 1;

c.0001101; three 1s; PE 1; PO 0

5.51 a. ABCDEFGHP 110101100;	P 1; Error in bit D.
b. ABCDEFGHP 110001101;	P 1; Error in
	parity bit.

5.49 a. 1111100; ﬁve 1s: PE 1; PO 0;		c. ABCDEFGHP 110001100; P 0; Data received
	INPUT
	nEVEN_ODD
INPUT	XOR
A
INPUT	XOR	XOR
B	XOR	XOR
B	XOR	XOR
	XOR	XOR
INPUT	XOR	OUTPUT	P_check
INPUT	XOR		P_check
C
INPUT
D
INPUT
E
INPUT
P_send

FIGURE ANS5.53

correctly.

d. ABCDEFGHP 110010100; P 0; Errors in bits E and F undetected

5.53See Figure ANS5.53.

Chapter 6
6.1	a. 11111;		b. 100000;	c. 11110;
	d. 101010;		e. 101100;	f. 1100100
6.3

			True	1’s	2’s
	Decimal	Magnitude Complement			Complement

a.	110		11101110	10010001	10010010
b.	67		01000011	01000011	01000011
c.	54		10110110	11001001	11001010
d.	93		11011101	10100010	10100011
e.	0		00000000	00000000	00000000
f.	1		10000001	11111110	11111111
g.	127		01111111	01111111	01111111
h.	127		11111111	10000000	10000001

6.5Largest: 011111112 12710; smallest: 100000002 12810

6.7Overﬂow in an 8-bit signed addition results if the sum is outside the range 128 sum 127. The sums in parts a. and f. do not generate an overﬂow. The sums in parts b., c., d., and e. do.

6.9	a. 3D;	True Binary
	Decimal	True Binary

	709	1011000101
	1889	11101100001
	2395	100101011011
	1259	10011101011
	3972	111110000100
	7730	1111000110010

8421 BCD	Excess-3

0111 0000 1001	1010 0011 1100
0001 1000 1000 1001	0100 1011 1011 1100
0010 0011 1001 0101	0101 0110 1100 1000
0001 0010 0101 1001	0100 0101 1000 1100
0011 1001 0111 0010	0110 1100 1010 0101
0111 0111 0011 0000	1010 1010 0110 0011

FIGURE ANS6.27

Answers to Selected Odd-Numbered Problems

797

b. 120;

57 41 52

49 4E 47 21

54 68 69 73

A R N I

SP T h i s

o m m a

SP e

4D 20

66 20

79 2E

SP 6 4

0 M

SP o f SP m

e m o

r y .

c.B1A;

d.FFF;

e.2A7F

6.11

6.15The sequence of codes yields the following text:

6.21A fast carry circuit is “ﬂatter”, but “wider” than a ripple carry circuit. There are more gate levels for an input change to propagate through in a ripple carry circuit. The ripple carry is thus slower. The limitation on a fast carry circuit is its width, both in the number of gates and on the number of inputs on the gates. Both factors increase with adder bit size.

6.23A carry is generated if the MSB of either A or B is HIGH AND the second bit of either A or B is HIGH AND the third bits of both A and B are HIGH.

6.25To generate all possible combinations of input for an 8-bit adder requires 216 65,536 combinations. (A simulation with one change every 40 ns would have an end time of 2.62144 ms.)

6.27See Figure ANS6.27

The transition from the sum FFF 000 FFF to FFF 001 000 (plus a carry) is given in the following table:

Time	Sum (Hex)	Sum (Binary) From a1 to:

0	FFF	1111 1111 1111

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