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Dueck R.Digital design with CPLD applications and VHDL.2000

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580

C H A P T E R 1 2 • Interfacing Analog and Digital Circuits

FIGURE 12.12

MC1408 Configured for

Unbuffered Analog Output

EXAMPLE 12.5

The DAC circuit in Figure 12.12 has the following component values: R14 R15

 

5.6 k ; RL 3.3 k . Vref ( ) is 8 V, and Vref ( ) is grounded.

 

Calculate the value of Vo for each of the following input codes: b7b6b5b4b3b2b1b0

 

00000000, 00000001, 10000000, 10100000, 11111111.

 

What is the resolution of this DAC?

 

Solution First, calculate the value of Iref.

 

Iref Vref ( )/R14

 

8 V/5.6 k 1.43 mA

 

Calculate the output current by using the binary fraction for each code. Multiply Io

 

by RL to get the output voltage.

 

b7b6b5b4b3b2b1b0 00000000

 

Io 0, Vo 0

 

b7b6b5b4b3b2b1b0 00000001

 

Io (1/256) (1.43 mA) 5.58 A

 

Vo (5.58 A)(3.3 k ) 18.4 mV

 

b7b6b5b4b3b2b1b0 10000000

 

Io (1/2) (1.43 mA) 714 A

 

Vo (714 A)(3.3 k ) 2.36 V

12.2 • Digital-to-Analog Conversion

581

b7b6b5b4b3b2b1b0 10100000

Io (1/2 1/8)(1.43 mA) (5/8)(1.43 mA) 893 A Vo (893 A)(3.3 k ) 2.95 V

b7b6b5b4b3b2b1b0 11111111

Io (255/256) (1.43 mA) 1.42 mA

Vo (1.42 mA)(3.3 k ) 4.70 V

Resolution is the same as the output resulting from the LSB: 18.4 mV/step

SECTION 12.2D REVIEW PROBLEM

12.5The output voltage range of an MC1408 DAC can be limited by grounding the Range pin. Why would we choose to do this?

Op Amp Buffering of MC1408

The MC1408 DAC will not drive much of a load on its own, particularly when the Range input is grounded. We can use an operational amplifier to increase the output voltage and current. This allows us to select the lower voltage range for faster switching while retaining the ability to drive a reasonable load. The output voltage is limited only by the op amp supply voltages. We use a 34071 high slew rate op amp for fast switching.

Figure 12.13 shows such a circuit. The 0.1- F capacitor decouples the 5-V supply. (The manufacturer actually recommends that the 5-V logic supply not be used as a reference voltage. It doesn’t matter for a demonstration circuit, but may introduce noise that is unacceptable in a commercial design.) The 75-pF capacitor is for phase compensation.

FIGURE 12.13

DAC With Op Amp Buffering

Vref 5 V

Va

 

RFA

4.7 k

0.1 F

 

 

 

 

R14A

 

RFB

12 V

 

 

 

 

 

 

2.7 k

 

10 k

 

 

 

R14B

 

 

I0

I0

 

 

 

 

 

 

 

 

5 k

 

 

 

 

 

 

(14)

 

(4)

 

Va

 

 

 

 

 

 

 

Vref( )

I0

 

12 V

 

 

(5)

(15)

1 k

 

b7

MSB

Vref( )

 

 

(6)

 

 

 

b6

 

 

 

R15

 

(7)

 

 

 

 

b5

 

 

 

 

 

(8)

 

 

 

 

 

b4

 

 

 

 

 

(9)

 

 

 

 

 

b3

MC1408

 

 

 

 

 

 

 

(10)

 

 

 

 

 

b2

 

 

 

 

 

(11)

 

 

(2)

 

 

b1

 

Range

 

 

(12)

 

(1)

 

 

b0

LSB

Ground

 

 

 

 

 

 

 

 

 

Comp

(16)

 

 

 

 

 

 

 

 

 

 

VCC

VEE

 

 

 

 

 

(13)

 

(3)

 

 

 

 

 

 

75 pF

 

 

5 V

12 V

 

 

582

C H A P T E R 1 2 • Interfacing Analog and Digital Circuits

Va is positive because the voltage drop across RF is positive with respect to the virtual ground at the op amp ( ) input. This feedback voltage is in parallel with (i.e., the same as) the output voltage, since both are measured from output to ground.

We can develop the formula for the analog voltage, Va, in three stages:

1. Calculate the reference current:

Iref Vref( )/R14

2. Determine the binary-weighted fraction of reference current to get DAC output current:

Io

=

b7

+

b6

+

b5

+

 

b4

+

b3

+

b2

+

 

b1

+

b0

 

Iref

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

8

16

 

32

64

128

256

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

=

b7

+

b6

+

b5

+

b4

 

+

b3

+

b2

+

b1

+

b0

 

Vref

 

 

2

 

4

 

8

 

16

 

 

 

32

 

64

 

128

 

256

 

R14

 

=

digital code Vref

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

256

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

 

 

 

 

 

 

 

 

3. Use Ohm’s law to calculate the op amp output voltage:

V

= I

R

= digital code

RF

V

a

 

o F

 

 

 

R

 

ref

 

 

 

256

 

 

 

 

 

 

 

 

14

 

 

The resistor values in the above formulae are the total resistances for the correspond-

ing part of the circuit. That is, R14 R14A R14B and RF RFA RFB. These both consist of a fixed and a variable resistor, which has two advantages: (a) The reference current

and output voltage can be independently adjusted within a specified range by the variable resistors. (b) The resistances defining the reference and feedback currents cannot go below a specified minimum value, determined by the fixed resistance, ensuring that excessive current does not flow into the reference input or the DAC output terminal.

Va can, in theory, be any positive value less than the op amp positive supply ( 12 V in this case). Any attempt to exceed this voltage makes the op amp saturate. The actual maximum value, if not the same as the op amp’s saturation voltage, depends on the values of RF and R14.

EXAMPLE 12.6

Describe a step-by-step procedure that calibrates the DAC circuit in Figure 12.13 so that it

 

has a reference current of 1 mA and a full-scale analog output voltage of 10 V, using only

 

a series of measurements of the analog output voltage. When the procedure is complete,

 

what are the resistance values in the circuit? What is the range of the DAC?

 

Solution Since the maximum output of the DAC is 1 LSB less than full scale, we must

 

indirectly measure the full scale value. We can do so by setting the digital input code to

 

10000000, which exactly represents the half-scale value of output current, and making ap-

 

propriate adjustments.

 

Set the variable feedback resistor to zero so that the output voltage is due only to the

 

fixed feedback resistor and the feedback current. Measure the output voltage of the circuit

 

and adjust R14B so that Va 2.35 volts. Ohm’s law tells us that this sets the feedback cur-

 

rent to IF 2.35 V/4.7 k 0.5 mA. Since the digital code is set for half scale, Iref 2 IF

 

1 mA.

 

Adjust RFB so that the half-scale output voltage is 5.00 V.

 

After adjustment, R14 2.7 k 2.3 k 5 k and RF 4.7 k 4.3 k 10

 

k . In both cases the variable resistors were selected so that their final values are about

 

half-way through their respective ranges.

 

The range of the DAC is 0 V to 9.961 V.

 

(FS 1 LSB 10 V (10 V/256) 9.961 V)

 

 

 

 

 

 

 

 

 

 

 

12.2

Digital-to-Analog Conversion

583

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXAMPLE 12.7

Figure 12.14 shows the circuit of an analog ramp (sawtooth) generator built from an

 

MC1408 DAC, an op amp, and an 8-bit synchronous counter. (A ramp generator has nu-

 

merous analog applications, such as sweep generation in an oscilloscope and frequency

 

sweep in a spectrum analyzer.)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vref 5 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10 k 4.7 k

 

 

 

 

 

 

 

0.1 F

 

 

2.7 k

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 k

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Va

 

 

 

 

CTR DIV 256

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vref( )

I0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q7

 

 

 

b7

Vref( )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q6

 

 

 

b6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q5

 

 

 

b5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q4

 

 

 

b4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MC1408

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q3

 

 

 

b3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q2

 

 

 

b2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

Q1

 

 

 

b1

Range

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q0

 

 

 

b0

Ground

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

VEE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

75 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 V

12 V

 

 

 

 

FIGURE 12.14

Example 16.5

DAC Ramp Generator

Briefly explain the operation of the circuit and sketch the output waveform. Calculate the step size between analog outputs resulting from adjacent codes. Assume that the DAC is set for 6-V output when the input code is 10000000.

Calculate the output sawtooth frequency when the clock is running at 1 MHz.

Solution The 8-bit counter cycles from 00000000 to 11111111 and repeats continuously. This is a total of 256 states.

The DAC output is 0 V for an input code of 00000000 and (12 V 1 LSB) for a code of 11111111. We know this because a code of 10000000 always gives an output voltage of half the full-scale value (6 V 12 V/2), and the maximum code gives an output that is one step less than the full-scale voltage. The step size is 12 V/256 steps 46.9 mV/step. The DAC output advances linearly from 0 to (12 V 1 LSB) in 256 clock cycles.

Figure 12.15 shows the analog output plotted against the number of input clock cycles. The ramp looks smooth at the scale shown. A section enlarged 32 times shows the analog steps resulting from eight clock pulses.

One complete cycle of the sawtooth waveform requires 256 clock pulses. Thus, if

fCLK 1 MHz, fo 1 MHz/256 3.9 kHz.

(Note that if we do not use a high slew rate op amp, the sawtooth waveform will not have vertical sides.)

584

C H A P T E R 1 2 • Interfacing Analog and Digital Circuits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIGURE 12.15

Example 12.7

Sawtooth Waveform Output of Circuit in Figure 12.14

Bipolar Operation of MC1408

Many analog signals are bipolar, that is, they have both positive and negative values. We can configure the MC1408 to produce a bipolar output voltage. Such a circuit is shown in Figure 12.16.

We can model the bipolar DAC as shown in Figure 12.16b. The amplitude of the

constant-current sink, Io, is set by Vref ( ), R14, and the binary value of the digital inputs. Is is determined by Ohm’s law: Is Vref ( )/R4.

The output voltage is set by the value of IF:

Va IF RF IF (RFA RFB)

By Kirchhoff’s current law:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Is IF Io 0

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IF Io Is

 

 

 

Thus, output voltage is given by:

 

 

 

 

 

 

Va (Io Is)RF Io RF Is RF

 

 

 

 

 

 

 

b7

b6

b5

b4

 

b3

b2

b1

b0

RF

 

 

 

 

Vref

 

2

4

8

16

 

32

64

128

256

R14

 

 

 

256

R14

ref

R4

 

ref

 

 

 

 

 

digital code

RF

 

V

 

RF

 

 

 

 

 

 

 

 

V

 

 

 

 

RF

Vref

R4

How do we understand the circuit operation from this mathematical analysis?

12.2 • Digital-to-Analog Conversion

585

FIGURE 12.16

MC1408 as a Bipolar D/A Converter

The current sink, Io, is a variable element. The voltage source, Vref ( ), remains constant. To satisfy Kirchhoff’s current law, the feedback current, IF, must vary to the same degree as Io. Depending on the value of Io with respect to Is, IF can be positive or negative.

We can get some intuitive understanding of the circuit operation by examining several cases of the equation Va.

586

C H A P T E R 1 2 • Interfacing Analog and Digital Circuits

Case 1: Io 0. This corresponds to the digital input b7b6b5b4b3b2b1b0 00000000. The output voltage is:

Va = (Io Is )RF = −Is RF = − RF Vref

R4

This is the maximum negative output voltage.

Case 2: 0 Io Is. The term (Io Is) is negative, so output voltage is also a negative value.

Case 3: Io Is. The output is given by:

 

Va (Io Is)RF 0

The digital code for this case could be any value, depending on the setting of R14. To set the

zero-crossing to half-scale, set the digital input to 10000000 and adjust R14 for 0 V.

Case 4: Io

Is. Since the term (Io Is) is positive, output voltage is positive. The largest

value of Io (and thus the maximum positive output voltage) corresponds to the input code

b7b6b5b4b3b2b1b0 11111111.

The magnitude of the maximum positive output voltage of this particular circuit is 2

LSB less

than the magnitude of the maximum negative voltage. Specifically, Va

(127/128)(RF/R4)(Vref) if R4 2R14.

 

To summarize:

 

 

 

 

 

 

 

 

 

Input Code

Output Voltage

 

 

 

 

 

00000000

Maximum negative*

 

 

 

 

 

10000000

0 V**

 

 

 

 

 

 

 

 

11111111

Maximum positive

 

 

 

 

 

*As adjusted by RFB

 

 

 

 

 

 

 

 

**As adjusted by R14B

 

 

 

 

 

 

 

 

Negative Range:

 

 

 

 

 

 

 

 

00000000 to 01111111

(128 codes)

 

 

Positive Range:

 

 

 

 

 

 

 

 

 

10000001 to 11111111

(127 codes)

 

 

Zero:

 

 

 

 

 

 

 

 

 

00000000

 

(001 code)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

256 codes

 

 

 

 

 

 

 

 

 

 

EXAMPLE 12.8

Calculate the values to which R14 and RF must be set to make the output of the bipolar

 

DAC in Figure 12.16 range from 12 V to ( 12 V 2 LSB). Describe the procedure you

 

would use to set the circuit output as specified.

 

 

Confirm that the calculated resistor settings generate the correct values of maximum

 

and minimum output.

 

 

 

 

 

 

 

 

Solution Set R14 so that the DAC circuit has an output of 0 V when input code is

 

b7b6b5b4b3b2b1b0 10000000. We can calculate the value of R14 as follows:

 

 

 

 

RF

V

RF

V

= 0

 

 

 

 

 

 

 

 

 

 

 

ref

 

 

ref

 

 

 

 

2R14

 

R4

 

 

 

 

 

 

 

 

 

 

12.2 •

Digital-to-Analog Conversion

587

The first term is set by the value of the input code. Solving for R14, we get:

 

 

1

 

 

1

 

RF Vref

= 0

 

 

 

 

 

 

 

 

2R14

 

 

 

 

R4

 

 

 

1

 

1

= 0

 

 

 

2R14

 

 

 

 

 

 

 

 

R4

 

 

 

1

 

=

1

 

 

 

 

 

 

2R14

R4

 

 

 

 

 

 

 

 

 

2R14 = R4

 

 

 

 

R14 = R4 /2 = 10 k/2 = 5 k

 

To set the maximum negative value, set the input code to 00000000 and adjust RFB for12 V. RFB RF RFA. Solve the following equation for RF:

 

 

 

 

 

RF

 

 

12 V

 

 

 

 

Vref

 

 

 

 

 

R4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RF

 

 

 

 

 

 

 

 

 

 

 

 

(5 V) 12 V

 

 

 

 

 

10 k

 

 

 

 

 

 

 

 

 

 

 

 

RF (12 V)(10 k )/5 V 24 k

 

 

 

 

 

RFB 24 k 18 k 6 k

Settings

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R14 R4/2 5 k for zero-crossing at half-scale.

 

 

 

RF 24 k for output of 12 V.

Check Output Range

 

 

 

 

 

 

 

 

 

 

For b7b6b5b4b3b2b1b0 00000000:

 

 

 

 

 

 

 

 

V

 

 

0

1

 

R

 

V

 

 

 

 

(24 k )(5 V)

 

 

 

 

 

12 V

 

 

a

R14

R4

 

F

 

ref

 

 

10 k

For b7b6b5b4b3b2b1b0 11111111:

 

 

 

 

 

V

 

 

 

255

 

1

 

R

 

V

 

 

 

 

 

 

 

 

 

a

 

256 R14

R4

 

 

 

F

 

ref

 

 

 

 

 

 

255

 

 

 

 

 

1

 

(24 k )(5 V) 11.906 V

 

 

 

 

 

 

 

 

(256)(5 k )

 

 

10 k

 

(Note: 12 V 2 LSB 12 V (12 V/128) 12 V 94 mV 11.906 V.)

SECTION 12.2E REVIEW PROBLEM

12.6Why is the actual maximum value of an 8-bit DAC less than its reference (i.e., its apparent maximum) voltage?

DAC Performance Specifications

A number of factors affect the performance of a digital-to-analog converter. The major factors are briefly described below.

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C H A P T E R

1 2 • Interfacing Analog and Digital Circuits

Analog output

Analog output

FS

 

 

 

 

 

 

 

FS

7/8 FS

 

 

 

 

 

 

 

7/8 FS

3/4 FS

 

Straight-line

 

 

 

 

3/4 FS

 

 

 

 

 

 

 

5/8 FS

 

approximation

 

 

 

5/8 FS

 

 

 

 

 

 

 

1/2 FS

 

 

 

 

 

 

 

1/2 FS

3/8 FS

 

 

 

 

 

 

 

3/8 FS

1/4 FS

 

 

 

 

 

 

 

1/4 FS

1/8 FS

 

 

 

 

 

 

 

1/8 FS

0

 

 

 

 

 

 

 

0

0

0

0

0

1

1

1

1

Digital

0

0

1

1

0

0

1

1

code

0

1

0

1

0

1

0

1

 

 

 

 

 

 

Output decreases

 

 

 

 

 

 

for increasing input

 

0

0

0

0

1

1

1

1

Digital

0

0

1

1

0

0

1

1

code

0

1

0

1

0

1

0

1

 

a. Ideal DAC response (monotonically increasing)

b. Nonmonotonically increasing

FIGURE 12.17

DAC Monotonicity

Monotonicity. The output of a DAC is monotonic if the magnitude of the output voltage increases every time the input code increases. Figure 12.17 shows the output of a DAC that increases monotonically and the output of a DAC that does not.

We show the output response of a DAC as a series of data points joined by a straightline approximation. One input code produces one voltage, so there is no value that corresponds to anything in between codes, but the straight-line approximation allows us to see a trend over the whole range of input codes.

Absolute accuracy. This is a measure of DAC output voltage with respect to its expected value.

Relative accuracy. Relative accuracy is a more frequently used measurement than absolute accuracy. It measures the deviation of the actual from the ideal output voltage as a fraction of the full-scale voltage. The MC1408 DAC has a relative accuracy of 12 LSB0.195% of full scale.

Settling time. The time required for the outputs to switch and settle to within 12 LSB when the input code switches from all 0s to all 1s. The MC1408 has a settling time of 300 ns for 8-bit accuracy, limiting its output switching frequency to 1/300 ns 3.33 MHz. Depending on the value of R4, the output resistor, the settling time of the MC1408 may increase to as much as 1.2 s when the Range input is open.

Gain error. Gain error primarily affects the high end of the output voltage range. If the gain of a DAC is too high, the output saturates before reaching the maximum output code. Figure 12.18 shows the effect of gain error in a 3-bit DAC. In the high gain response, the last two input codes (110 and 111) produce the same output voltage.

FIGURE 12.18

DAC Gain Errors

FIGURE 12.19

DAC Linearity Error

 

12.2 • Digital-to-Analog Conversion

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Analog output

Saturated output

 

for high codes

 

 

 

FS

 

 

7/8 FS

Gain too high

 

 

 

3/4 FS

5/8 FS "Normal" gain

1/2 FS

3/8 FS

1/4 FS

Gain too low 1/8 FS (max. code does

not reach (FS 1 LSB))

0

0

0

0

0

1

1

1

1

Digital

0

0

1

1

0

0

1

1

code

0

1

0

1

0

1

0

1

 

Linearity error. This error is present when the analog output does not follow a straightline increase with increasing digital input codes. Figure 12.19 shows this error. A linearity error of more than 12 LSB can result in a nonmonotonic output. For example, in Figure 12.17b, the transition from 010 to 011 should result in an output change of 1 LSB. Instead, it results in a change of 12 LSB. This is an error of 112 LSB, resulting in a nonmonotonic output.

In Figure 12.19, the code for 011 has a linearity error of 12 LSB and the adjacent code (100) has a linearity error of 12 LSB, yielding a flat output for the two codes. This makes it impossible to distinguish the value of input code for that analog output value.

Analog output

FS

 

 

 

 

 

 

 

 

7/8 FS

 

 

 

 

 

 

 

 

3/4 FS

 

 

Linear

 

 

 

 

 

 

 

 

response

 

 

 

 

5/8 FS

 

 

 

 

 

 

 

 

1/2 FS

1/2 LSB

 

 

 

 

 

 

 

 

 

 

 

Nonlinear

 

 

 

 

 

 

 

 

3/8 FS

 

 

 

 

 

response

 

 

 

 

 

1/2 LSB

 

 

 

 

 

 

 

 

 

1/4 FS

 

 

 

 

 

 

 

 

1/8 FS

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

0

0

0

0

1

1

1

1

Digital

0

0

1

1

0

0

1

1

code

0

1

0

1

0

1

0

1