Dueck R.Digital design with CPLD applications and VHDL.2000

SN54/74LS00

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)

FIGURE 11.3

74LS00 Data (2 of 2) Reprinted with permission of Motorola.

Solution When the output is in the LOW state, the output current is given by IOL, which has a maximum value of 8 mA. The output voltage, VOL, is specified for a value of 4 mA and for 8 mA. Since the output condition is specified for maximum IOL (8 mA),

502 C H A P T E R 1 1 • Logic Gate Circuitry

The 74XX00 NAND gate data is sufficient to represent any logic functions having “normal” output current within its particular logic family. This data can be used for most gate or flip-flop circuits within the family. Some specialized devices with higher-current outputs (e.g., 74XX244 octal tristate buffers) have a different set of electrical characteristics within their family.

In the following sections of the chapter, we will use a NAND gate from each of three device families (74LS00, 74HC00A, and 74HCT00A) for illustrating the general principles of the various electrical characteristics. Devices from other families will also be used in examples and problems. Data sheets for the various devices are included in Appendix C.

SECTION 11.1 REVIEW PROBLEM

11.1What are the maximum values of voltage and current we can expect at the output of a 74LS00 NAND gate when both inputs are LOW?

11.2Propagation Delay

K E Y T E R M S

Propagation delay occurs because the output of a logic gate or flip-flop cannot respond instantaneously to changes at its input. There is a short delay, on the order of several nanoseconds, between input change and output response. This is largely due to the charging and discharging of capacitances inherent in the switching transistors of the gate or flipflop.

Figure 11.4 shows propagation delay in two gates: a 74XX00 NAND gate and a 74XX08 AND gate. Each gate has an identical input waveform, a LOW-HIGH-LOW pulse. After each input transition, the output changes after a short delay, tp.

FIGURE 11.4

Propagation Delay in NAND and AND Gates

Two delays are shown for each gate: tpLH and tpHL. The LH and HL subscripts show the direction of change at the gate output; LH indicates that the output goes from LOW to

HIGH, and HL shows the output changing from HIGH to LOW.

Propagation delay is the time between input and output voltages passing through a standard reference value. The reference voltage for standard TTL is 1.5 V. LSTTL and CMOS have different reference voltages, as follows.

N O T E

Propagation Delay for Various Logic Families:

LSTTL: Time from 1.3 V at input to 1.3 V at output.

Other TTL: Time from 1.5 V at input to 1.5 V at output.

CMOS: Time from 50% of maximum input to 50% of maximum output.

*Temperature range (74F00): 0°C to 70°C.

**VCC 4.5 V, temperature range (74HC00): 55°C to 25°C.

***VCC 5 V, temperature range (74HCT00): 55°C to 25°C.

As indicated by the notes for Table 11.3, propagation delay (and other parameters) vary with certain operating conditions, such as ambient temperature and power supply voltage. Always make sure that the operating conditions are correctly specified when looking up a data sheet parameter.

All gates in Example 11.3 have the same logic function (2-input NAND), but different propagation delay times. We might ask, “Why not always use the advanced Schottky TTL gate (74AS00), since it is the fastest?” The main reason is that it has the highest power dissipation of the gates shown. We wouldn’t know this without looking up other specs on the data sheet. (We will learn how to do this later in the chapter.) Thus, it is important to make design decisions based on complete information, not just one parameter.

504 C H A P T E R 1 1 • Logic Gate Circuitry

Propagation Delay in Logic Circuits

A circuit consisting of two or more gates or flip-flops has a propagation delay that is the sum of delays in the input-to-output path. Delays in gates that do not affect the circuit output are disregarded. Figure 11.5 shows how propagation delay works in a simple logic circuit consisting of a 74HC08 AND gate and a 74HC32 OR gate. Changes at inputs A and B must propagate through both gates to affect the output. The total delay in such a case is the sum of tp1 and tp2. A change at input C must pass only through gate 2. The circuit delay resulting from this change is only tp2.

FIGURE 11.5

Propagation Delays in a Logic Gate Circuit

The timing diagram in Figure 11.5 shows the changes at inputs A, B, and C and the resulting transitions at all gate outputs.

Assume VCC 4.5 V and temperature range is 55°C to 25°C.

1.When A goes LOW, AB, the output of gate 1, also goes LOW after a maximum delay of

tpHL 15 ns. This makes Y go LOW after a further delay of up to tpHL 15 ns. Total delay: tp tpHL1 tpHL2 15 ns 15 ns 30 ns, max.

2.The HIGH-to-LOW transition at input B has no effect, since there is no difference between 0 1 and 0 0. AB is already LOW.

3.The LOW-to-HIGH transition at input C makes Y go HIGH after a maximum delay of tpLH2 15 ns.

SECTION 11.2 REVIEW PROBLEM

11.2Assume the gates in Figure 11.5 are replaced by a 74LS08 AND gate and a 74LS32 OR gate. Repeat the calculations of for the propagation delays if the waveforms of Figure 11.5 are applied to the circuit. The data sheets for the 74LS08 and 74LS32 are found in Appendix C.

11.3 Fanout

K E Y T E R M S

Fanout The number of load gates that a logic gate output is capable of driving without possible logic errors.

Driving gate A gate whose output supplies current to the inputs of other gates.

Load gate A gate whose input current is supplied by the output of another gate.

Sourcing A terminal on a gate or flip-flop is sourcing current when the current flows out of the terminal.

Sinking A terminal on a gate or flip-flop is sinking current when the current flows into the terminal.

We have assumed that logic gates are able to drive any number of other logic gates. Since gates are electrical devices with finite current-driving capabilities, this is obviously not the case. The number of gates (“loads”) a logic gate can drive is referred to as its fanout.

N O T E

Fanout is simply an application of Kirchhoff’s current law: The algebraic sum of currents at a node must be zero. Thus, the fanout of a logic gate is limited by:

a.The maximum current its output can supply safely in a given logic state (IOH or IOL), and

b.The current requirements of the load to which it is connected (IIH or IIL).

Figure 11.6 shows the fanout of an AND gate when its output is in the HIGH and LOW states. The AND gate, or driving gate, supplies current to the inputs of the other four gates, which are called the load gates.

Each load gate requires a fixed amount of input current, depending on which state it is in. The sum of these input currents equals the current supplied by the driving gate. The

FIGURE 11.6

Driving Gates and Load Gates

Solution Since there are two identical load gates in the circuits of Figure 11.8, the driving gate output current will be twice the load gate input current.

IOL 2 0.4 mA 0.8 mA.

IOH 2 ( 20 A) 40 A.

Figure 11.9 shows the extension of the circuits in Figures 11.7 and 11.8, where the number of load gates is the maximum that can be driven by the driving gate. This is the condition used to calculate fanout.

b. High output on driving gate

FIGURE 11.9

Output Current to Fanout Calculation

If the load gates each represent the same load, then by Kirchhoff’s current law (KCL):

IOL IIL1 IIL2 … IILnL nL IIL

and IOH IIH1 IIH2 … IIHnH nH IIH

The fanout of the driving gate in the LOW and HIGH states can be calculated as:

By convention, current entering a gate (IIH, IOL) is denoted as positive, and current leaving a gate (IIL, IOH) is denoted as negative. When current is leaving a gate, we say the gate is sourcing current. When current is entering a gate, we say the gate is sinking current.

Note that the output of a gate does not always source current, nor does an input always sink current. The current direction changes for the HIGH and LOW states at the same terminal. The reason for this will become apparent when we study the circuitry of logic gate inputs and outputs.

Solution We must consider the following cases:

a.When the output of the driving gate is LOW

b.When the output of the driving gate is HIGH

Output LOW:

IOL 8 mA (sinking)

IIL 0.4 mA (sourcing) nL 8 mA/0.4 mA 20

Output HIGH:

IOH 0.4 mA (sourcing) IIH 20 A (sinking)

nH 0.4 mA/20 A 20

Since nL nH, fanout is 20.

We disregard the negative sign in our calculations, since the input current of the load gate and output current of the driving gate are actually in the same direction. For example, even though IOH is leaving the driving gate (negative), IIH is entering the load gates (positive). These currents flow in the same direction. If we include the minus sign in our calculation, we get a negative value of fanout, which is meaningless.

The fanout in both HIGH and LOW states is the same in this case, but that is not always so. If the values of HIGHand LOW-state fanout are different, the smallest value must be used. For example, if a gate can drive four loads in the HIGH state or eight in the LOW state, the fanout of the driving gate is four loads. If we attempt to drive eight loads, we can’t guarantee enough driving current to supply all loads in both states.

If a gate from one logic family is used to drive gates from another logic family, we must use the output parameters (IOL, IOH) for the driving gate and the input parameters (IIL, IIH) for the load gates.

Output LOW:

IOL 8 mA (sinking) IIL 2 mA (sourcing) nL 8 mA/2 mA 4

Output HIGH:

IOH 0.4 mA (sourcing) IIH 50 A (sinking)

nH 0.4 mA/50 A 8

Since nL nH, fanout nL 4.