Dueck R.Digital design with CPLD applications and VHDL.2000

7.15A pump motor can be started at two different locations

with momentary-contact pushbuttons S1 and S2. It can be stopped by momentary-contact pushbuttons ST1 and ST2. As in Problem 7.4, a RUN input on the motor controller must be kept HIGH to keep the motor running. After the motor is stopped, a timer prevents the motor from starting for 5 minutes.

Draw a circuit block diagram showing how an SR latch and some additional gating logic can be used in

FIGURE 7.76

Problem 7.16

Waveforms

FIGURE 7.77

Problem 7.17

Waveforms

such an application. The timer can be shown as a block activated by the STOP function. Assume that the timer output goes HIGH for 5 minutes when activated.

7.16The S and R waveforms in Figure 7.76 are applied to two different gated latches. The ENABLE waveforms for the

latches are shown as EN1 and EN2. Draw the output waveforms Q1 and Q2, assuming that S, R, and EN are all active HIGH. Which output is least prone to synchronization errors? Why?

7.17Figure 7.77 represents the waveforms of the EN and D inputs of a 4-bit transparent latch. Complete the timing diagram by drawing the waveforms for Q1 to Q4.

7.18An electronic direction finder aboard an aircraft uses a 4- bit number to distinguish 16 different compass points as follows:

Problems 321

The output of the direction finder is stored in a 4-bit latch so that the aircraft flight path can be logged by a computer. The latch is periodically updated by a continuous pulse on the latch enable line.

Figure 7.78 shows a sample reading of the direction finder’s output as presented to the latch. (Problem continues . . .)

N

S

NNE

N

E

ES

a.Complete the timing diagram by filling in the data for the Q outputs.

b.Based on the completed timing diagram of Figure 7.78, make a rough sketch of the aircraft’s flight path for the monitored time.

7.19Write a VHDL file for an 8-bit latch, using LATCH primitives. Create a simulation file that demonstrates the operation of all eight bits.

7.20Write a VHDL file for an 8-bit latch, using a component from the Library of Parameterized Modules. Create a simulation file that tests the latch for all eight bits.

Section 7.4 Edge-Triggered D Flip-Flops

7.21The waveforms in Figure 7.79 are applied to the inputs of a positive edge-triggered D flip-flop and a gated D latch.

Complete the timing diagram where Q1 is the output of the flip-flop and Q2 is the output of the gated latch. Ac-

FIGURE 7.79

Problem 7.21

Waveforms

FIGURE 7.80

Problem 7.22

Waveforms

FIGURE 7.81

Problem 7.23

Waveforms

count for any differences between the Q1 and Q2 waveforms.

7.22Complete the timing diagram for a positive edge-trig- gered D flip-flop if the waveforms shown in Figure 7.80 are applied to the flip-flop inputs.

7.23Repeat Problem 7.22 for the waveforms shown in Figure 7.81.

7.24Repeat Problem 7.22 for the waveforms shown in Figure 7.82.

7.25Draw a logic diagram of a D flip-flop configured for toggle mode. (Hint: The D input must always be the opposite of the Q output.)

7.26Write a VHDL file that defines a 12-bit D flip-flop with a clock common to all flip-flops, using MAX PLUS II primitives. The component declaration for the DFF component is as follows:

FIGURE 7.82

Problem 7.24

Waveforms

COMPONENT DFF

END COMPONENT;

Disregard the clrn (active-LOW clear) and prn (ac- tive-LOW preset) ports for this problem. (Hint: you may have to use a component declaration in your file that only declares the ports d, clk, and q.)

Problems 323

7.27Write a VHDL file that creates a 12-bit D flip-flop, using the LPM component lpm_ff. (This component is instantiated as a D flip-flop by default. The required LPM component port names are: data, clock, and q.)

Section 7.5 Edge-Triggered JK Flip-Flops

7.28The waveforms in Figure 7.83 are applied to a negative edge-triggered JK flip-flop. Complete the timing diagram by drawing the Q waveform.

7.29Repeat Problem 7.28 for the waveforms in Figure 7.84.

7.30Given the inputs x, y, and z to the circuit in Figure 7.85, draw the waveform for output Q.

FIGURE 7.83

Problem 7.28

Waveforms

FIGURE 7.84

Problem 7.29

Waveforms

FIGURE 7.85

Problem 7.30 Inputs to Circuit

CLK

J

K

Q

CLK

J

K

Q

CLK

x

y

z

Q

7.31Assume that all flip-flops in Figure 7.86 are initially set.

Draw a timing diagram showing the CLK, Q0, Q1, and Q2 waveforms when eight clock pulses are applied. Make a

table showing each combination of Q2, Q1, and Q0. What pattern do the outputs form over the period shown on the timing diagram?

7.32Refer to the JK flip-flop circuit in Figure 7.87. Is the circuit synchronous or asynchronous? Explain your answer.

7.33Assume all flip-flops in the circuit in Figure 7.87 are reset. Analyze the operation of the circuit when six-

teen clock pulses are applied by making a table showing the sequence of states of Q3Q2Q1Q0, beginning at 0000.

7.34Draw a timing diagram showing the sequence of states from the table derived in Problem 7.33.

7.35The waveforms shown in Figure 7.88 are applied to a negative edge-triggered JK flip-flop. The flip-flop’s Preset and Clear inputs are active LOW. Complete the timing diagram by drawing the output waveforms.

7.36Repeat Problem 7.35 for the waveforms in Figure 7.89.

7.37Create a MAX PLUS II Graphic Design File for the synchronous circuit in Figure 7.87. Modify the circuit to add an asynchronous Master Reset function. Create a simulation file to verify the circuit operation.

7.38Modify the gdf created in Problem 7.37 to include a Master Reset function and an asynchronous preset function that will set the state of the circuit to Q3Q2Q1Q0 1010 when activated. Create a simulation file to verify the circuit operation.

7.39The term asynchronous is sometimes used to refer to the configuration of a circuit (e.g., a 3-bit asynchronous counter) and sometimes to a type of input to a device (e.g., an asynchronous clear input). Briefly explain how these two usages are similar and how they are different.

7.40Write a VHDL file for a 12-bit D flip-flop that uses MAX PLUS II DFF primitives, similar to that in Problem 7.26. Include active-LOW asynchronous clear (CLRN)

CLK

T

Q

FIGURE 7.90

Problem 7.42

Timing Diagram

and preset (PRN) inputs. Create a simulation file to verify the operation of your design.

7.41Write a VHDL file for a 12-bit D flip-flop with asynchronous preset and clear, using the LPM component lpm_ff, similar to that in Problem 7.27. Required ports: data, clock, aclr (asynchronous clear), aset (asynchronous set), and q. Ports aset and aclr are active-HIGH. Add two signals to the VHDL design to make them active-LOW. Create a simulation file to verify the operation of your design.

Section 7.6 Edge-Triggered T Flip-Flops

7.42The T and CLK waveforms for a positive-edge triggered T flip-flop is shown in Figure 7.90. Complete the timing diagram.

7.43The T and CLK waveforms for a positive-edge triggered T flip-flop is shown in Figure 7.91. Complete the timing diagram.

7.44Refer to the synchronous circuit in Figure 7.87. Create a MAX PLUS II Graphic Design File for a circuit with the same function, using T flip-flops rather than JK flipflops. Include an asynchronous reset input in the circuit. Create a simulation file to test the operation of the circuit.

7.45Write a VHDL file that implements the circuit you drew in Problem 7.44. Use TFF primitives in the design.

Section 7.7 Timing Parameters

7.46Use a TTL or high-speed CMOS data sheet, as appropriate, to look up the setup and hold times of the following devices:

a.74LS74A

b.74HC76

c.74LS76A

d.74LS107A

e.74ALS112A

f.74HC112

7.47Draw a timing diagram showing the setup and hold times for a 74LS76A flip-flop.

7.48Draw timing diagrams (to scale) showing setup and hold times, minimum CLK and CLR pulse widths, recovery time, and propagation delay times from CLK and CLR for both 74LS107A and 74HC107 flip-flops.

7.49Write names and values of the JK flip-flop timing parameters illustrated in Figure 7.92.

FIGURE 7.92

Problem 7.49

Timing Parameters

7.50Repeat Problem 7.49 for the timing diagram in Figure 7.93.

FIGURE 7.93

Problem 7.50

Timing Diagram

Section 7.1

7.1 The latch resets (i.e., Q goes LOW) upon receiving the first reset pulse. At that point, the latch is already reset, so further pulses are ignored.

Section 7.2

7.2 The NOR latch has active-HIGH inputs. If you make both inputs HIGH, you are attempting to set and reset the latch at the same time, which is a contradictory action. A NAND latch has active-LOW inputs. Therefore, if both inputs are HIGH, neither the set nor reset function activates and there is no change on the latch output.

Section 7.3

7.3

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY altera;

USE altera.maxplus2.ALL;

ENTITY lch16prm IS

ARCHITECTURE a OF lch16prm IS

BEGIN

—— Instantiate a latch from a MAX PLUS II primitive latch4:

FOR i IN 15 downto 0 GENERATE latch_primitive: latch

PORT MAP (d d in (i),

ena enable, q q out (i) ); END GENERATE;

END a;

Section 7.4

7.4 The edge detector circuit in the clock circuit accounts for the operational difference between a D flip-flop and a D latch. It works by using the difference in internal delay times between the gates that comprise the flip-flop’s clock input circuit.

Section 7.5

7.5 The flip-flops in asynchronous circuits are not all clocked at the same time; they are asynchronous with respect to the system clock. The flip-flops in a synchronous circuit have a common clock connection, which makes them synchronous to the system clock. The disadvantage to asynchronous circuits is that the internal delays of flip-flops can lead to unwanted intermediate states, since the flip-flops do not all change at the same time.

O U T L I N E

8.1Programmable Sum-of-Products Arrays

8.2PAL Fuse Matrix and Combinational Outputs

8.3PAL Outputs with Programmable Polarity

8.4PAL Devices with Programmable Polarity

8.5Universal PAL and Generic Array Logic

8.6MAX7000S CPLD

8.7FLEX10K CPLD

C H A P T E R O B J E C T I V E S

Upon successful completion of this chapter, you will be able to:

•Draw a diagram showing the basic hardware conventions for a sum-of- products-type programmable logic device.

•Describe the structure of a programmable array logic (PAL) AND matrix.

•Draw fuses on the logic diagram of a PAL to implement simple logic functions.

•Describe the structures of combinational, programmable polarity, and registered PAL outputs.

•Determine the number and type of outputs from a PAL/GAL part number.

•Explain the structure of an output logic macrocell (OLMC).

•State differences between Universal PAL and generic array logic (GAL) and standard PAL.

•Interpret the logic diagrams of Universal PAL and GAL devices to determine the number of outputs and product terms and the type of control signals available in a device.

•Interpret block diagrams to determine the basic structure of an Altera MAX7000S CPLD, including macrocell configuration, Logic Array Blocks (LABs), control signals, and product term expanders.

•State the differences between PLDs based on sum-of-products (SOP) architecture versus look-up table (LUT) architecture.

•Interpret block diagrams to determine the basic structure of a logic element in an Altera FLEX10K CPLD, including look-up tables, cascade chains, carry chains, and control signals.

•Interpret block diagrams to determine how a logic element in a FLEX10K device relates to the overall structure of the device.

•Interpret block diagrams to determine how logic array blocks and embedded array blocks relate to the overall structure of a FLEX10K CPLD.

In the past several chapters, we have been using Altera’s MAX PLUS II software to make circuit designs for downloading into a complex programmable logic device (CPLD). We have treated this device as a black box—something whose function we design, but whose

structure we do not really understand. In this chapter, we will look inside the box. ■