Cooper K.Engineering a compiler

Figure 10.11: A clustered register-set machine

dures, the allocator must deal with parameter binding mechanisms and with the side e ects of linkage conventions. Each of these creates new situations for the allocator. Call-by-reference parameter binding can link otherwise independent live ranges in distinct procedures together into a single interprocedural live range. Furthermore, they can introduce ambiguity into the memory model, by creating multiple names that can access a single memory location. (See the discussion of “aliasing” in Chapter 13.) Register save/restore conventions introduce mandatory spills that might, for a single intraprocedural live range, involve multiple memory locations.

10.6.2Partitioned Register Sets

New complications can arise from new hardware features. For example, consider the non-uniform costs that arise on machines with partitioned register sets. As the number of functional units rises, the number of registers required to hold operands and results rises. Limitations arise in the hardware logic required to move values between registers and functional units. To keep the hardware costs manageable, some architects have partitioned the register set into smaller register files and clustered functional units around these partitions. To retain generality, the processor typically provides some limited mechanism for moving values between clusters. Figure 10.11 shows a highly abstracted view of such a processor. Assume, without loss of generality, that each cluster has an identical set of functional units and registers, except for their unique names.

Machines with clustered register sets layer a new set of complications onto the register assignment problem. In deciding where to place lri in the register set, the allocator must understand the availability of registers in each cluster, the cost and local availability of the inter-cluster transfer mechanism, and the specific functional units that will execute the operations that reference lri. For example, the processor might allow each cluster to generate one o -cluster register reference per cycle, with a limit of one o -cluster transfer out of each cluster each cycle. With this constraint, the allocator must pay attention to

lying problems are almost all np-complete, the solutions tend to be sensitive to small decisions, such as how ties between identically ranked choices are broken.

We have made progress on register allocation by resorting to paradigms that give us leverage. Thus, graph-coloring allocators have been popular, not because register allocation is identical to graph coloring, but rather because coloring captures some of the critical aspects of the global problem. In fact, most of the improvements to the coloring allocators have come from attacking the points where the coloring paradigm does not accurately reflect the underlying problem, such as live range splitting, better cost models, and improved methods for live range splitting.

Questions

1.The top-down local allocator is somewhat naive in its handling of values. It allocates one value to a register for the entire basic block.

(a)An improved version might calculate live ranges within the block and allocate values to registers for their live ranges. What modifications would be necessary to accomplish this?

(b)A further improvement might be to split the live range when it cannot be accommodated in a single register. Sketch the data structures and algorithmic modifications that would be needed to (1) break a live range around an instruction (or range of instructions) where a register is not available, and to (2) re-prioritize the remaining pieces of the live range.

(c)With these improvements, the frequency count technique should generate better allocations. How do you expect your results to compare with using Best’s algorithm? Justify your answer.

2.When a graph-coloring global allocator reaches the point where no color is available for a particular live range, lri, it spills or splits that live range. As an alternative, it might attempt to re-color one or more of lri’s neighbors. Consider the case where lri, lrj I and lri, lrk I, butlrj , lrk I. If lrj and lrk have already been colored, and have received di erent colors, the allocator might be able to re-color one of them to the other’s color, freeing up a color for lri.

(a)Sketch an algorithm for discovering if a legal and productive recoloring exists for lri.

(b)What is the impact of your technique on the asymptotic complexity of the register allocator?

(c)Should you consider recursively re-coloring lrk’s neighbors? Explain your rationale.

3.The description of the bottom-up global allocator suggests inserting spill code for every definition and use in the spilled live range. The top-down

global allocator first breaks the live range into block-sized pieces, then combines those pieces when the result is unconstrained, and finally, assigns them a color.

(a)If a given block has one or more free registers, spilling a live range multiple times in that block is wasteful. Suggest an improvement to the spill mechanism in the bottom-up global allocator that avoids this problem.

(b)If a given block has too many overlapping live ranges, then splitting a spilled live range does little to address the problem in that block. Suggest a mechanism (other than local allocation) to improve the behavior of the top-down global allocator inside blocks with high demand for registers.

Chapter Notes

Best’s algorithm, detailed in Section 10.2.2 has been rediscovered repeatedly. Backus reports that Best described the algorithm to him in the mid-1950’s, making it one of the earliest algorithms for the problem [3, 4]. Belady used the same ideas in his o ine page replacement algorithm, min, and published it in the mid-1960’s [8]. Harrison describes these ideas in connection with a regional register allocator in the mid-1970’s [36]. Fraser and Hanson used these ideas in the lcc compiler in the mid-1980s. [28]. Liberatore et al. rediscovered and reworked this algorithm in the late 1990s [42]. They codified the notion of spilling clean values before spilling dirty values.

Frequency counts have a long history in the literature. . . .

The connection between graph coloring and storage allocation problems that arise in a compiler was originally suggested by the Soviet mathematician Lavrov [40]. He suggested building a graph that represented conflicts in storage assignment, enumerating its various colorings, and using the coloring that required the fewest colors. The Alpha compiler project used coloring to pack data into memory [29, 30].

Top-down graph-coloring begins with Chow. His implementation worked from a memory-to-memory model, so allocation was an optimization that improved the code by eliminating loads and stores. His allocator used an imprecise interference graph, so the compiler used another technique to eliminate extraneous copy instructions. The allocator pioneered live range splitting, using the scheme described on page 273 Larus built a top-down, priority-based allocator for Spur-Lisp. It used a precise interference graph and operated from a register-to-register model.

The first coloring allocator described in the literature was due to Chaitin and his colleagues at Ibm [22, 20, 21]. The description of a bottom-up allocator in Section 10.4.5 follows Chaitin’s plan, as modified by Briggs et al. [17]. Chaitin’s contributions include the fundamental definition of interference, the algorithms for building the interference graph, for coalescing, and for handling spills. Briggs modified Chaitin’s scheme by pushing constrained live ranges

onto the stack rather than spilling them directly; this allowed Briggs’ allocator to color a node with many neighbors that used few colors. Subsequent improvements in bottom-up coloring have included better spill metrics [10], methods for rematerializing simple values [16], iterated coalescing [33], methods for spilling partial live ranges [9], and methods for live range splitting [26]. The large size of precise interference graphs led Gupta, So a, and Steele to work on splitting the graph with clique separators [34]. Harvey et al. studied some of the tradeo s that arise in building the interference graph [25].

The problem of modeling overlapping register classes, such as singleton registers and paired registers, requires the addition of some edges to the interference graph. Briggs et al. describe the modifications to the interference graph that are needed to handle several of the commonly occurring cases [15]. Cytron & Ferrante, in their paper “What’s in a name?”, give a polynomial-time algorithm for performing register assignment. It assumes that, at each instruction, | Live | < k. This corresponds to the assumption that the code has already been allocated.

Beatty published one of the early papers on regional register allocation [7]. His allocator performed local allocation and then used a separate technique to remove unneeded spill code at boundaries between local allocation regions— particularly at loop entries and exits. The hierarchical coloring approach was described by Koblenz and Callahan and implemented in the compiler for the Tera computer [19]. The probabilistic approach was presented by Proebsting and Fischer[44].

Figure 11.2: Precedence Graph for the Example

and a delay. For a node n, the instruction corresponding to n must execute on a functional unit of type type(n) and it requires delay(n) cycles to complete. The example in Figure 11.1 produces the precedence graph shown in Figure 11.2.

Nodes with no predecessors in the precedence graph, such as a, c, e, and g in the example, are called leaves of the graph. Since the leaves depend on no other operations, they can be scheduled at any time. Nodes with no successors in the precedence graph, such as i in the example, are called roots of the graph. A precedence graph can have multiple roots. The roots are, in some sense, the most constrained nodes in the graph because they cannot execute until all of their ancestors execute. With this terminology, it appears that we have drawn the precedence graph upside down—at least with relationship to the syntax trees and abstract syntax trees used earlier. Placing the leaves at the top of the figure, however, creates a rough correspondence between placement in the drawing and eventual placement in the scheduled code. A leaf is at the top of the tree because it can execute early in the schedule. A root is at the bottom of the tree because it must execute after each its ancestors.

Given a precedence graph for its input code fragment, a schedule S maps each node n N into a non-negative integer that denotes the cycle in which it should be issued, assuming that the first operation issues in cycle one. This provides a clear and concise definition of an instruction: the ith instruction is the set of operations n S(n) = i. A schedule must meet three constraints.

1.S(n) ≥ 0, for each n N . This constraint forbids operations from being issued before execution starts. Any schedule that violates this constraint

is not well formed. For the sake of uniformity, the schedule must also have at least one operation n with S(n ) = 1.

2.If (n1, n2) E, S(n1) + delay(n1) ≤ S(n2). This constraint enforces correctness. It requires that an operation cannot be issued until the operations that produce its arguments have completed. A schedule that violates this rule changes the flow of data in the code and is likely to produce in-