Timing Diagrams

Figure 89. General Timings

Note: nWAIT, APE, ALE and ABE are all HIGH during the cycle shown. Tcdel is the delay (on either edge) from MCLK changing to ECLK changing.

190 Timing Diagrams

Timing Diagrams

Figure 90. ALE Address Control

MCLK

ALE

A[31:0], nRW, LOCK, nOPC, nTRANS, MAS[1:0]

Note: Tald is the time by which ALE must be driven LOW in order to latch the current address in phase 2. If ALE is driven low after Tald, then a new address will be latched.

Figure 91. APE Address Control

MCLK

Figure 92. ABE Address Control

MCLK

191

Figure 93. Bidirectional Data Write Cycle

MCLK

Tnen

nENOUT

Tnenh

D[31:0]

Note: DBE is HIGH and nENIN is LOW during the cycle shown.

Figure 94. Bidirectional Data Read Cycle

BL[3:0]

Note: DBE is HIGH and nENIN is LOW during the cycle shown.

192 Timing Diagrams

Figure 97. Unidirectional Data Write Cycle

MCLK

Tnen

nENOUT

Tdohu

DOUT[31:]

Tdoutu

Figure 98. Unidirectional Data Read Cycle

MCLK

Tnen

nENOUT

DIN[31:0]

Tdisu Tdihu

BL[3:0]

Figure 99. Configuration Pin Timing

MCLK

BIGEND

194 Timing Diagrams

Timing Diagrams

Note: Normally, nMREQ and SEQ become valid Tmsd after the falling edge of MCLK. In this cycle the ARM has been busy-waiting, waiting for a coprocessor to complete the instruction. If CPA and CPB change during phase 1, the timing of nMREQ and SEQ will depend on Tcpms. Most systems should be able to generate CPA and CPB during the previous phase 2, and so the timing of nMREQ and SEQ will always be Tmsd.

Figure 101. Exception Timing

MCLK

Tabts Tabth

ABORT

Tis Tim

nFIQ, IRQ

Trs Trm

nMREQ, SEQ

195

Figure 103. Breakpoint Timing

MCLK

BREAKPT

Tbcems

nCPI, nEXEC, nMREQ, SEQ

Note: BREAKPT changing in the LOW phase of MCLK to signal a watchpointed store can affect nCPI, nEXEC, nMREQ, and SEQ in the LOW phase of MCLK.

Figure 104. TCK-ECLK Relationship

MCLK

ECLK

196 Timing Diagrams

Timing Diagrams

Note: The ARM core is not clocked by the HIGH phase of MCLK enveloped by nWAIT. Thus, during the cycles shown, nMREQ and SEQ change once, during the first LOW phase of MCLK, and A[31:0] change once, during the second HIGH phase of MCLK. For reference, ph2 is shown. This is the internal clock from which the core times all its activity. This signal is included to show how the high phase of the external MCLK has been removed from the internal core clock.

197

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© Atmel Corporation 1999.

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Rev. 0673B–01/99