Disabling ICEBreaker

ICEBreaker may be disabled by wiring the DBGEN input LOW.

When DBGEN is LOW, BREAKPT and DBGRQ to the core are forced LOW, DBGACK from the ARM7TDMI is also forced LOW and the IFEN input to the core is forced HIGH, enabling interrupts to be detected by ARM7TDMI.

When DBGEN is LOW, ICEBreaker is also put into a lowpower mode.

ICEBreaker Timing

The EXTERN1 and EXTERN0 inputs are sampled by ICEBreaker on the falling edge of ECLK. Sufficient set-up and hold time must therefore be allowed for these signals.

Programming Restriction

The ICEBreaker watchpoint units should only be programmed when the clock to the core is stopped. This can be achieved by putting the core into the debug state.

The reason for this restriction is that if the core continues to run at ECLK rates when ICEBreaker is being programmed at TCK rates, it is possible for the BREAKPT signal to be asserted asynchronously to the core.

This restriction does not apply if MCLK and TCK are driven from the same clock, or if it is known that the breakpoint or watchpoint condition can only occur some time after ICEBreaker has been programmed.

Note: This restriction does not apply in any event to the Debug Control or Status Registers.