Cycle Types

All memory transfer cycles can be placed in one of four categories:

1.Non-sequential cycle. ARM7TDMI requests a transfer to or from an address which is unrelated to the address used in the preceding cycle.

2.Sequential cycle. ARM7TDMI requests a transfer to or from an address which is either the same as the address in the preceding cycle, or is one word or halfword after the preceding address.

3.Internal cycle. ARM7TDMI does not require a transfer, as it is performing an internal function and no useful prefetching can be performed at the same time.

4.Coprocessor register transfer. ARM7TDMI wishes to use the data bus to communicate with a coprocessor, but does not require any action by the memory system.

These four classes are distinguishable to the memory system by inspection of the nMREQ and SEQ control lines

(see Table 31). These control lines are generated during phase 1 of the cycle before the cycle whose characteristics they forecast, and this pipelining of the control information gives the memory system sufficient time to decide whether or not it can use a page mode access.

Table 31. Memory Cycle Types

Figure 58 shows the pipelining of the control signals, and suggests how the DRAM address strobes (nRAS and nCAS) might be timed to use page mode for S-cycles. Note that the N-cycle is longer than the other cycles. This is to allow for the DRAM precharge and row access time, and is not an ARM7TDMI requirement.

When an S-cycle follows an N-cycle, the address will always be one word or halfword greater than the address used in the N-cycle. This address (marked “a” in the above diagram) should be checked to ensure that it is not the last in the DRAM page before the memory system commits to the S-cycle. If it is at the page end, the S-cycle cannot be performed in page mode and the memory system will have to perform a full access.

The processor clock must be stretched to match the full access. When an S-cycle follows an I-cycle, the address will be the same as that used in the I-cycle. This fact may be used to start the DRAM access during the preceding cycle, which enables the S-cycle to run at page mode speed whilst performing a full DRAM access. This is shown in Figure 59.

Address Timing

ARM7TDMI’s address bus can operate in one of two configurations - pipelined or depipelined, and this is controlled by the APE input signal. The configurability is provided to ease the design in of ARM7TDMI to both SRAM and DRAM based systems.

It is a requirement SRAMs and ROMs that the address be held stable throughout the memory cycle. In a system con-

Figure 60. ARM7TDMI De-Pipelined Addresses

MCLK

APE

nMREQ SEQ

A[31:0]

D[31:0]

In a DRAM based system, it is desirable to obtain the address from ARM7TDMI as early as possible. When APE is HIGH, ARM7TDMI's address becomes valid in the MCLK high phase before the memory cycle to which it refers. This timing allows longer for address decoding and the generation of DRAM control signals. Figure 61 shows the effect on the timing when APE is HIGH.

taining SRAM and ROM only, APE may be tied permanently LOW, producing the desired address timing. This is shown in Figure 60.

Note: APE affects the timing of the address bus A[31:0], plus nRW, MAS[1:0], LOCK, nOPC and nTRANS.

Many systems will contain a mixture of DRAM and SRAM/ROM. To cater for the different address timing requirements, APE may be safely changed during the low phase of MCLK. Typically, APE would be held at one level during a burst of sequential accesses to one type of memory. When a non-sequential access occurs, the timing of most systems enforce a wait state to allow for address decoding. As a result of the address decode, APE can be driven to the correct value for the particular bank of memory being accessed. The value of APE can be held until

the memory control signals denote another non-sequential access.

By way of an example, Figure 62 shows a combination of accesses to a mixed DRAM / SRAM system. Here, the SRAM has zero wait states, and the DRAM has a 2:1 N- cycle / S-cycle ratio. A single wait state is inserted for address decode when a non-sequential access occurs. Typical, externally generated DRAM control signals are also shown.

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Previous ARM processors included the ALE signal, and this is retained for backwards compatibility. This signal also allows the address timing to be modified to achieve the same results as APE, but in an asynchronous manner. To obtain clean MCLK low timing of the address bus by this mechanism, ALE must be driven HIGH with the falling edge of MCLK, and LOW with the rising edge of MCLK.

Figure 63. SRAM Compatible AddressTiming

MCLK

APE

ALE

nMREQ SEQ

A[31:0]

D[31:0]

Note: If ALE is to be used to change address timing, then APE must be tied HIGH. Similarly, if APE is to be used, ALE must be tied HIGH.

Memory

ALE can simply be the inverse of MCLK but the delay from MCLK to ALE must be carefully controlled such that the Tald timing constraint is achieved. Figure 63 shows how ALE can be used to achieve SRAM compatible address timing. Refer to Timing Diagrams on page 189 for details of the exact timing constraints.

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