- •Introduction
- •ARM7TDMI Architecture
- •The THUMB Concept
- •THUMB’s Advantages
- •ARM7TDMI Block Diagram
- •ARM7TDMI Core Diagram
- •ARM7TDMI Functional Diagram
- •Key to signal types
- •Processor Operating States
- •Switching State
- •Entering THUMB state
- •Entering ARM state
- •Memory Formats
- •Big endian format
- •Little endian format
- •Instruction Length
- •Data Types
- •Operating Modes
- •Registers
- •The ARM state register set
- •The THUMB state register set
- •The relationship between ARM and THUMB state registers
- •Accessing Hi registers in THUMB state
- •The Program Status Registers
- •The condition code flags
- •The control bits
- •Exceptions
- •Action on entering an exception
- •Action on leaving an exception
- •Exception entry/exit summary
- •Notes
- •Abort
- •Software interrupt
- •Undefined instruction
- •Exception vectors
- •Exception priorities
- •Not all exceptions can occur at once:
- •Interrupt Latencies
- •Reset
- •Instruction Set Summary
- •Format summary
- •Instruction summary
- •The Condition Field
- •Branch and Exchange (BX)
- •Instruction cycle times
- •Assembler syntax
- •Using R15 as an operand
- •Examples
- •Branch and Branch with Link (B, BL)
- •The link bit
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Data Processing
- •CPSR flags
- •Shifts
- •Instruction specified shift amount
- •Register specified shift amount
- •Immediate operand rotates
- •Writing to R15
- •Using R15 as an operand
- •TEQ, TST, CMP and CMN opcodes
- •Instruction cycle times
- •Assembler syntax
- •where:
- •Examples
- •PSR Transfer (MRS, MSR)
- •Operand restrictions
- •Reserved bits
- •Example
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Multiply and Multiply-Accumulate (MUL, MLA)
- •If the operands are interpreted as signed
- •If the operands are interpreted as unsigned
- •Operand restrictions
- •CPSR flags
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Multiply Long and Multiply-Accumulate Long (MULL,MLAL)
- •Operand restrictions
- •CPSR flags
- •Instruction cycle times
- •For signed instructions SMULL, SMLAL:
- •For unsigned instructions UMULL, UMLAL:
- •Assembler syntax
- •where:
- •Examples
- •Single Data Transfer (LDR, STR)
- •Offsets and auto-indexing
- •Shifted register offset
- •Bytes and words
- •Little endian configuration
- •Big endian configuration
- •Restriction on the use of base register
- •Example:
- •Data aborts
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Halfword and Signed Data Transfer(LDRH/STRH/LDRSB/LDRSH)
- •Offsets and auto-indexing
- •Halfword load and stores
- •Signed byte and halfword loads
- •Endianness and byte/halfword selection
- •Little endian configuration
- •Big endian configuration
- •Data aborts
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Block Data Transfer (LDM, STM)
- •The register list
- •Addressing modes
- •Address alignment
- •LDM with R15 in transfer list and S bit set (Mode changes)
- •STM with R15 in transfer list and S bit set (User bank transfer)
- •R15 not in list and S bit set (User bank transfer)
- •Use of R15 as the base
- •Inclusion of the base in the register list
- •Data aborts
- •Aborts during STM instructions
- •Aborts during LDM instructions
- •Instruction cycle times
- •Assembler syntax
- •Addressing mode names
- •Examples
- •Single Data Swap (SWP)
- •Bytes and words
- •Data aborts
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Software Interrupt (SWI)
- •Return from the supervisor
- •Comment field
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Supervisor code
- •Coprocessor Data Operations (CDP)
- •The coprocessor fields
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Coprocessor Data Transfers (LDC, STC)
- •The coprocessor fields
- •Addressing modes
- •Address alignment
- •Data aborts
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Coprocessor Register Transfers (MRC, MCR)
- •The coprocessor fields
- •Transfers to R15
- •Transfers from R15
- •Instruction cycle times
- •Assembler syntax
- •Examples
- •Undefined Instruction
- •Instruction cycle times
- •Assembler syntax
- •Instruction Set Examples
- •Using the conditional instructions
- •Using conditionals for logical OR
- •Absolute value
- •Multiplication by 4, 5 or 6 (run time)
- •Combining discrete and range tests
- •Division and remainder
- •Overflow detection in the ARM7TDMI
- •Pseudo-random binary sequence generator
- •Multiplication by constant using the barrel shifter
- •Multiplication by 2^n (1,2,4,8,16,32..)
- •Multiplication by 2^n+1 (3,5,9,17..)
- •Multiplication by 2^n-1 (3,7,15..)
- •Multiplication by 6
- •Multiply by 10 and add in extra number
- •General recursive method for Rb := Ra*C, C a constant:
- •Loading a word from an unknown alignment
- •Format Summary
- •Opcode Summary
- •Format 1: move shifted register
- •Operation
- •Instruction cycle times
- •Examples
- •Format 2: add/subtract
- •Operation
- •Instruction cycle times
- •Examples
- •Format 3: move/compare/add/subtract immediate
- •Operations
- •Instruction cycle times
- •Examples
- •Format 4: ALU operations
- •Operation
- •Instruction cycle times
- •Examples
- •Format 5: Hi register operations/branch exchange
- •Operation
- •Instruction cycle times
- •The BX instruction
- •Examples
- •Using R15 as an operand
- •Format 6: PC-relative load
- •Operation
- •Instruction cycle times
- •Examples
- •Format 7: load/store with register offset
- •Operation
- •Instruction cycle times
- •Examples
- •Format 8: load/store sign-extended byte/halfword
- •Operation
- •Instruction cycle times
- •Examples
- •Format 9: load/store with immediate offset
- •Operation
- •Instruction cycle times
- •Examples
- •Format 10: load/store halfword
- •Operation
- •Instruction cycle times
- •Examples
- •Format 11: SP-relative load/store
- •Operation
- •Instruction cycle times
- •Examples
- •Format 12: load address
- •Operation
- •Instruction cycle times
- •Examples
- •Format 13: add offset to Stack Pointer
- •Operation
- •Instruction cycle times
- •Examples
- •Format 14: push/pop registers
- •Operation
- •Instruction cycle times
- •Examples
- •Format 15: multiple load/store
- •Operation
- •Instruction cycle times
- •Examples
- •Format 16: conditional branch
- •Operation
- •Instruction cycle times
- •Examples
- •Format 17: software interrupt
- •Operation
- •Instruction cycle times
- •Examples
- •Format 18: unconditional branch
- •Operation
- •Examples
- •Format 19: long branch with link
- •Operation
- •Instruction cycle times
- •Examples
- •Instruction Set Examples
- •Multiplication by a constant using shifts and adds
- •General purpose signed divide
- •Thumb code
- •ARM code
- •Division by a constant
- •Explanation of divide-by-constant ARM code
- •ARM code
- •THUMB code
- •Overview
- •Cycle Types
- •Address Timing
- •Data Transfer Size
- •Instruction Fetch
- •Memory Management
- •Locked Operations
- •Stretching Access Times
- •The ARM Data Bus
- •The External Data Bus
- •The unidirectional data bus
- •The bidirectional data bus
- •Example system: The ARM7TDMI Testchip
- •Overview
- •Interface Signals
- •Coprocessor present/absent
- •Busy-waiting
- •Pipeline following
- •Data transfer cycles
- •Register Transfer Cycle
- •Privileged Instructions
- •Idempotency
- •Undefined Instructions
- •Debug Interface
- •Overview
- •Debug Systems
- •Debug Interface Signals
- •Entry into debug state
- •Entry into debug state on breakpoint
- •Entry into debug state on watchpoint
- •Entry into debug state on debug-request
- •Action of ARM7TDMI in debug state
- •Scan Chains and JTAG Interface
- •Scan limitations
- •Scan chain 0
- •Scan chain 1
- •Scan Chain 2
- •The JTAG state machine
- •Reset
- •Pullup Resistors
- •Instruction Register
- •Public Instructions
- •EXTEST (0000)
- •SCAN_N (0010)
- •INTEST (1100)
- •IDCODE (1110)
- •BYPASS (1111)
- •CLAMP (0101)
- •HIGHZ (0111)
- •CLAMPZ (1001)
- •SAMPLE/PRELOAD (0011)
- •RESTART (0100)
- •Test Data Registers
- •Bypass register
- •ARM7TDMI device identification (ID) code register
- •Operating mode:
- •Instruction register
- •Scan chain select register
- •Scan chains 0,1 and 2
- •Scan chain 0 and 1
- •Scan chain 0
- •Scan chain 1
- •Scan chain 3
- •ARM7TDMI Core Clocks
- •Clock switch during debug
- •Clock switch during test
- •Determining the Core and System State
- •Determining the core’s state
- •Determining system state
- •Exit from debug state
- •The PC’s Behaviour During Debug
- •Breakpoint
- •Watchpoints
- •Watchpoint with another exception
- •Debug request
- •System speed access
- •Summary of return address calculations
- •Priorities / Exceptions
- •Breakpoint with prefetch abort
- •Interrupts
- •Data aborts
- •Scan Interface Timing
- •Debug Timing
- •Overview
- •The Watchpoint Registers
- •Programming and reading watchpoint registers
- •Using the mask registers
- •The control registers
- •Programming Breakpoints
- •Hardware breakpoints:
- •Software breakpoints:
- •Hardware breakpoints
- •Software breakpoints
- •Setting the breakpoint
- •Clearing the breakpoint
- •Programming Watchpoints
- •The Debug Control Register
- •Debug Status Register
- •Coupling Breakpoints and Watchpoints
- •Example
- •CHAINOUT signal
- •RANGEOUT signal
- •Example
- •Disabling ICEBreaker
- •ICEBreaker Timing
- •Programming Restriction
- •Debug Communications Channel
- •Debug comms channel registers
- •Communications via the comms channel
- •Introduction
- •Branch and Branch with Link
- •THUMB Branch with Link
- •Branch and Exchange (BX)
- •Data Operations
- •Multiply and Multiply Accumulate
- •Load Register
- •Store Register
- •Load Multiple Registers
- •Store Multiple Registers
- •Data Swap
- •Software Interrupt and Exception Entry
- •Coprocessor Data Operation
- •Coprocessor Data Transfer (from memory to coprocessor)
- •Coprocessor Data Transfer (from coprocessor to memory)
- •Coprocessor Register Transfer (Load from coprocessor)
- •Coprocessor Register Transfer (Store to coprocessor)
- •Undefined Instructions and Coprocessor Absent
- •Unexecuted Instructions
- •Instruction Speed Summary
- •Timing Diagrams
Coprocessor Register Transfers (MRC, MCR)
The instruction is only executed if the condition is true. The various conditions are defined in Table 6. The instruction encoding is shown in Figure 36.
This class of instruction is used to communicate information directly between ARM7TDMI and a coprocessor. An example of a coprocessor to ARM7TDMI register transfer (MRC) instruction would be a FIX of a floating point value held in a coprocessor, where the floating point number is converted into a 32 bit integer within the coprocessor, and the result is then transferred to ARM7TDMI register. A
FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer (MCR).
An important use of this instruction is to communicate control information directly from the coprocessor into the ARM7TDMI CPSR flags. As an example, the result of a comparison of two floating point values within a coprocessor can be moved to the CPSR to control the subsequent flow of execution.
Figure 36. Coprocessor Register Transfer Instructions
31 |
28 |
27 |
24 |
23 |
21 |
20 |
19 |
16 |
15 |
12 |
11 |
8 |
7 |
5 |
4 |
3 |
0 |
Cond |
|
1110 |
|
CP Opc |
L |
CRn |
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Rd |
|
CP# |
|
CP |
1 |
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CRm |
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Coprocessor operand register
Coprocessor information
Coprocessor number
ARM source/destination register
Coprocessor source/destination register
Load/Store bit
0 = Store to Co-Processor
1 = Load from Co-Processor
Coprocessor operation mode
Condition field
The coprocessor fields
The CP# field is used, as for all coprocessor instructions, to specify which coprocessor is being called upon.
The CP Opc, CRn, CP and CRm fields are used only by the coprocessor, and the interpretation presented here is derived from convention only. Other interpretations are allowed where the coprocessor functionality is incompatible with this one. The conventional interpretation is that the CP Opc and CP fields specify the operation the coprocessor is required to perform, CRn is the coprocessor register which is the source or destination of the transferred information, and CRm is a second coprocessor register which may be involved in some way which depends on the particular operation specified.
Transfers to R15
When a coprocessor register transfer to ARM7TDMI has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the N, Z, C and V flags respectively. The other bits of the transferred word are ignored, and the PC and other CPSR bits are unaffected by the transfer.
Transfers from R15
A coprocessor register transfer from ARM7TDMI with R15 as the source register will store the PC+12.
Instruction cycle times
MRC instructions take 1S + (b+1)I +1C incremental cycles to execute, where S, I and C are as defined in Cycle Types.
MCR instructions take 1S + bI +1C incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop.
70 Instruction Set 