Instruction Set Summary
Format summary
The ARM instruction set formats are shown below.
Figure 10. ARM Instruction Set Formats
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2 |
1 |
0 |
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Data Processing / |
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Cond |
0 |
0 |
I |
Opcode |
S |
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Rn |
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Rd |
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Operand 2 |
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PSR Transfer |
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Multiply |
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Cond |
0 |
0 |
0 |
0 |
0 |
0 |
A |
S |
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Rd |
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Rn |
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Rs |
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1 |
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0 |
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0 |
1 |
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Rm |
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Multiply Long |
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Cond |
0 |
0 |
0 |
0 |
1 |
U |
A |
S |
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RdHi |
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RdLo |
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Rn |
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1 |
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0 |
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0 |
1 |
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Rm |
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Single Data Swap |
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Cond |
0 |
0 |
0 |
1 |
0 |
B |
0 |
0 |
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Rn |
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Rd |
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0 |
0 |
0 |
0 |
1 |
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0 |
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0 |
1 |
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Rm |
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Branch and Exchange |
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Cond |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
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0 |
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0 |
1 |
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Rn |
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Halfword Data Transfer: |
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Cond |
0 |
0 |
0 |
P |
U |
0 |
W |
L |
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Rn |
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Rd |
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0 |
0 |
0 |
0 |
1 |
S |
H |
1 |
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Rm |
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register offset |
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Halfword Data Transfer: |
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Cond |
0 |
0 |
0 |
P |
U |
1 |
W |
L |
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Rn |
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Rd |
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Offset |
1 |
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S |
H |
1 |
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Offset |
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immediate offset |
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Single Data Transfer |
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Cond |
0 |
1 |
I |
P |
U |
B |
W |
L |
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Rn |
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Rd |
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Offset |
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Undefined |
Cond |
0 |
1 |
1 |
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1 |
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Block Data Transfer |
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Cond |
1 |
0 |
0 |
P |
U |
S |
W |
L |
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Rn |
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Register List |
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Branch |
Cond |
1 |
0 |
1 |
L |
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Offset |
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Coprocessor Data |
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Cond |
1 |
1 |
0 |
P |
U |
N |
W |
L |
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Rn |
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CRd |
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CP# |
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Offset |
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Coprocessor Data |
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Cond |
1 |
1 |
1 |
0 |
CP Opc |
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CRn |
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CRd |
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CP# |
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CP |
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0 |
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CRm |
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Operation |
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Coprocessor Register |
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Cond |
1 |
1 |
1 |
0 |
CP Opc |
L |
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CRn |
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Rd |
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CP# |
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CP |
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1 |
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CRm |
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Software Interrupt |
Cond |
1 |
1 |
1 |
1 |
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Ignored by processor |
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 |
9 |
8 |
7 |
6 |
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5 |
4 |
3 |
2 |
1 |
0 |
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Note: Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for instance a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations.
28 Instruction Set 
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Instruction Set |
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Instruction summary |
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Table 5. The ARM Instruction Set |
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Mnemonic |
Instruction |
Action |
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See Page |
ADC |
Add with carry |
Rd := Rn + Op2 + Carry |
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34 |
ADD |
Add |
Rd := Rn + Op2 |
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34 |
AND |
AND |
Rd := Rn AND Op2 |
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34 |
B |
Branch |
R15 := address |
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32 |
BIC |
Bit Clear |
Rd := Rn AND NOT Op2 |
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34 |
BL |
Branch with Link |
R14 := R15, R15 := address |
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32 |
BX |
Branch and Exchange |
R15 := Rn, |
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31 |
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T bit := Rn[0] |
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CDP |
Coprocesor Data Processing |
(Coprocessor-specific) |
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66 |
CMN |
Compare Negative |
CPSR flags := Rn + Op2 |
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34 |
CMP |
Compare |
CPSR flags := Rn - Op2 |
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34 |
EOR |
Exclusive OR |
Rd := (Rn AND NOT Op2) |
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34 |
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OR (op2 AND NOT Rn) |
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LDC |
Load coprocessor from memory |
Coprocessor load |
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68 |
LDM |
Load multiple registers |
Stack manipulation (Pop) |
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56 |
LDR |
Load register from memory |
Rd := (address) |
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48, 52 |
MCR |
Move CPU register to |
cRn := rRn {<op>cRm} |
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70 |
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coprocessor register |
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MLA |
Multiply Accumulate |
Rd := (Rm * Rs) + Rn |
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44, 46 |
MOV |
Move register or constant |
Rd : = Op2 |
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34 |
MRC |
Move from coprocessor |
Rn := cRn {<op>cRm} |
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70 |
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register to CPU register |
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MRS |
Move PSR status/flags to |
Rn := PSR |
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40 |
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register |
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MSR |
Move register to PSR |
PSR := Rm |
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40 |
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status/flags |
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MUL |
Multiply |
Rd := Rm * Rs |
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44, 46 |
MVN |
Move negative register |
Rd := 0xFFFFFFFF EOR Op2 |
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34 |
ORR |
OR |
Rd := Rn OR Op2 |
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34 |
RSB |
Reverse Subtract |
Rd := Op2 - Rn |
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34 |
RSC |
Reverse Subtract with Carry |
Rd := Op2 - Rn - 1 + Carry |
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34 |
SBC |
Subtract with Carry |
Rd := Rn - Op2 - 1 + Carry |
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34 |
STC |
Store coprocessor register to mem- |
address := CRn |
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68 |
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ory |
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STM |
Store Multiple |
Stack manipulation (Push) |
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56 |
STR |
Store register to memory |
<address> := Rd |
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48, 52 |
SUB |
Subtract |
Rd := Rn - Op2 |
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34 |
SWI |
Software Interrupt |
OS call |
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64 |
SWP |
Swap register with memory |
Rd := [Rn], [Rn] := Rm |
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62 |
TEQ |
Test bitwise equality |
CPSR flags := Rn EOR Op2 |
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34 |
TST |
Test bits |
CPSR flags := Rn AND Op2 |
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34 |
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