
- •Preface
- •About this document
- •Intended audience
- •Organization
- •Typographical conventions
- •Timing diagram conventions
- •Further reading
- •ARM publications
- •Feedback
- •Feedback on this document
- •Feedback on the ARM PrimeCell VC-SDRAM Controller
- •1 Introduction
- •1.1.2 General information
- •2 Functional Overview
- •2.1.2 AHB bus interface
- •2.1.3 Optional features
- •2.1.4 DMA ports
- •2.1.5 Pad interface
- •2.2.1 External bus
- •2.2.2 Internal bus
- •2.2.4 Locking virtual channels to DMA and bus interface ports
- •3 Programmer’s Model
- •3.1 About the programmer’s model
- •3.3 Register descriptions
- •3.3.1 Configuration registers
- •3.3.2 Refresh timer register
- •3.3.4 Lock registers
- •3.4 System initialization
- •3.5 Address mapping
- •3.5.2 Mapping the DMA address buses
- •A.1 On-chip signals
- •A.1.1 AMBA AHB signals
- •A.1.3 DMA ports
- •A.1.4 Miscellaneous
- •A.2 Off-chip signals
- •A.2.1 VC-SDRAM memory interface signals

Feedback
ARM Limited welcomes feedback on both the ARM PrimeCell VC-SDRAM
Controller (PL070) and on the documentation.
Feedback on this document
If you have any comments on this document, please send an email to errata@arm.com giving:
•the document title
•the document number
•the page number(s) to which your comments refer
•a concise explanation of your comments.
General suggestions for additions and improvements are also welcome.
Feedback on the ARM PrimeCell VC-SDRAM Controller
If you have any comments or suggestions about this product, please contact your supplier giving:
•the product name
•a concise explanation of your comments.
viii |
© Copyright ARM Limited 1999. All rights reserved. |
ARM DDI 0162B |

Contents
ARM PrimeCell Technical Reference Manual
Preface
About this document |
......................................................................................................iv |
Further reading.............................................................................................................. |
vii |
Feedback ..................................................................................................................... |
viii |
Chapter 1 |
Introduction |
|
|
|
1.1 |
About the ARM PrimeCell VC-SDRAM Controller (PL070)........................... |
1-2 |
Chapter 2 |
Functional Overview |
|
|
|
2.1 |
ARM PrimeCell VC-SDRAM Controller (PL070) overview............................ |
2-2 |
|
2.2 |
Overview of a VC-SDRAM, ASIC/ASSP, unified memory system................ |
2-7 |
Chapter 3 |
Programmer’s Model |
|
|
|
3.1 |
About the programmer’s model..................................................................... |
3-2 |
|
3.2 |
Summary of PrimeCell VC-SDRAM Controller registers............................... |
3-3 |
|
3.3 |
Register descriptions .................................................................................... |
3-4 |
|
3.4 |
System initialization .................................................................................... |
3-10 |
|
3.5 |
Address mapping ........................................................................................ |
3-11 |
Appendix A |
ARM PrimeCell VC-SDRAM Controller (PL070) Signal Descriptions |
|
|
|
A.1 |
On-chip signals ............................................................................................. |
A-2 |
|
A.2 |
Off-chip signals ............................................................................................. |
A-8 |
ARM DDI 0162B |
© Copyright ARM Limited 1999. All rights reserved. |
ix |

x |
© Copyright ARM Limited 1999. All rights reserved. |
ARM DDI 0162B |