Index

A

C

Functional blocks

2-1

AMBA

Control registers 2-6

I

APB

2-5

APB signals A-2

D

Internal reference clock

2-2

B

Interrupt generation logic

2-6

Double-buffered UART interface 2-2

Interrupts 3-29

combined UART 3-31

Baud rate divisor

2-11, 3-10

E

modem status

3-30

Baud rate generator 1-2, 2-2, 2-5

receive timeout

3-31

Baud rate, setting

3-10

transmit 3-30

Baud16

2-5, 2-8

Error bits

2-13

UARTEINTR

3-31

Bits

UARTINTR

3-31

asynchronous communication

1-2

UARTMSINTR

3-30

error

2-13

F

UARTRTINTR

3-31

parity 1-2

UARTRXINTR

3-30

start

1-2

FIFO 1-2

UARTTXINTR

3-30

stop

1-2

disabling

2-13

IrDA SIR

BnRES

A-3

masking

1-2

block 2-3

BUSY

2-12

receive

2-6

enabling serial communication 2-3

transmit

1-2, 2-5, 2-12

physical layer

2-14

Free-running counters 2-5

receive decoder

2-9

ARM DDI 0183E

Copyright © 2000, 2001 ARM Limited. All rights reserved.

Index-1

transmit encoder

2-8

O

S

IrDA SIR ENDEC

1-2, 1-3, 2-3, 2-14

IrLPBaud16

2-5, 2-8, 2-14

Overrun bit 2-13

Signal descriptions

A-1

Overrun error

2-13

Signals

L

APB

A-2

P

to pad

A-5

Line break

SIRIN 2-3, 2-14

2-7

Synchronizing logic

detection

1-3

Parameters

Synchronizing registers

2-7

generation

1-3

programmable 1-3

Line control register

2-2

PCLK 2-7, 2-10, A-3

T

Logic

PRESETn 2-10

interrupt generation 2-6

PrimeCell UART

receiver

2-6

block diagram 2-4

Test logic 2-7

synchronizing 2-7

features 1-2

Test vectors

2-13

test 2-7

functional blocks

2-1

Transmission parameters

2-11

transmitter

2-6

operation 2-10

Transmit FIFO

2-5, 2-12

register descriptions 3-5

Transmit mode

2-2

M

signal descriptions

A-1

Transmitter logic 2-6

Maskable interrupts

2-2, 2-6

R

U

Masking

modem status interrupts

1-2

Receive FIFO

2-6

UARTCLK

2-2, 2-5, 2-7, 2-8, 2-10,

receive timeout

1-2

Receive mode

2-2

2-14, A-3

Modem

Receiver logic

2-6

UARTILPR

2-14

control functions

1-3

Register block

2-5

UARTRXD

2-3, 2-12

control lines 2-2

Register descriptions

3-5

UARTRXDMACLR

4-6

status input signals 2-2

Registers

UARTTDR

4-5

Modes

UARTCR

3-15

UARTTXD

2-3

low-power IrDA mode

2-14

UARTDMACR 3-23

UARTTXDMACLR

4-6

normal IrDA mode 2-14

UARTDR

3-5

receive

2-2

UARTFBRD

3-10

Numerics

transmit

2-2

UARTFR

3-8

UARTIBRD

3-10

N

UARTICR

3-22

16C550 UART

1-4, 2-2

UARTIFLS

3-17

UARTIMSC

3-18

nSIROUT

2-3, 2-14

UARTLCR_H 3-12

nUARTCTS

2-3, 3-30

UARTMIS

3-21

nUARTDCD

3-30

UARTPCellID0-3 3-26

nUARTDSR

3-30

UARTPeriphID0-3 3-23

nUARTRI

3-30

UARTRIS

3-19

nUARTRST

2-10, A-3

UARTRSR/UARTECR

3-7

nUARTRTS

2-3

Reserved locations 3-2

Index-2

Copyright © 2000, 2001 ARM Limited. All rights reserved.

ARM DDI 0183E