Functional Overview

2.3PrimeCell RTC operation

The operation of the PrimeCell RTC is described in the following sections:

•Interface reset

•Clock signals

•PrimeCell RTC operation.

2.3.1Interface reset

The PrimeCell RTC requires three reset signals to reset the various parts, nRTCRST, nPOR, and PRESETn. PRESETn must be asserted LOW for a period long enough to reset the slowest block in the on-chip system, and then be taken HIGH again. The PrimeCell RTC requires PRESETn to be asserted LOW for at least one period of PCLK. PRESETn is used to reset most of the logic clocked by PCLK.

The interrupt output RTCINTR is LOW after reset.

Power on Reset (nPOR) resets the match register and offset register, and must therefore be deasserted synchronously to PCLK.

nRTCRST is used to reset the logic in the CLK1HZ domain, and must therefore be deasserted synchronously to CLK1HZ. In addition, nRTCRST must only be generated as a result of nPOR, and not a soft reset. Failure to do this results in the loss of the RTC value. PRESETn can be generated as a result of either nPOR or a soft reset.

The values of registers after reset are defined in Chapter 3 Programmer’s Model.

2.3.2Clock signals

The period of the clock signal CLK1HZ must be selected to determine the resolution of the RTC. For example, selecting a 1Hz clock signal produces a one second counter resolution.

There is a constraint on the ratio of clock frequencies for PCLK to CLK1HZ. The frequency of PCLK must be greater than three times the frequency of CLK1HZ.

FPCLK > 3 x FCLK1HZ.

2.3.3PrimeCell RTC operation

After reset, values must be written to the load register RTCLR and match register

RTCMR.

The counter increments by 1 on the rising edge of CLK1HZ.

To enable the interrupt, set the RTCIMSC register by writing a 1.

Functional Overview

When the counter and match registers are identical, and the interrupt is not masked, the interrupt RTCINTR is asserted HIGH. The interrupt is cleared by writing 1 to the interrupt clear register RTCICR.

By using a 1Hz clock signal for CLK1HZ, the counter increments in one second intervals. This can be used to implement a real-time clock function in software as well as a basic alarm time function.