11.Dedicated microprocessors
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Chapter 11 – Dedicated Microprocessors |
Page 21 of 25 |
D0 = Q0next = s0(Start=1) + s2(n>1)
=Q2'Q1'Q0' (Start=1) + Q2'Q1Q0' (n>1)
D1 = Q1next = s1 + s2(n>1) + s3
=Q2'Q1'Q0 + Q2'Q1Q0' (n>1) + Q2'Q1Q0
D2 = Q2next = s2(n>1)'
=Q2'Q1Q0' (n>1)'
Load = Q2'Q1'Q0 |
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Count = Q2'Q1Q0 |
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Done = Q2Q1'Q0' |
♦ |
Example 11.7
We want to construct a circuit at the FSMD level using a custom datapath for the following problem:
Input an 8-bit number. Output a 1 if the number has the same number of 0’s and 1’s, otherwise, output a 0. e.g. the number 10111011 will produce a 0 output, whereas, the number 00110011 will produce a 1 output.
The high-level pseudo code for solving the problem is as follows:
input |
n |
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count |
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0 |
// for counting the number of zeros |
while |
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if |
LSB(n) = 1 |
// least significant bit of n |
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count = count + 1 |
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else |
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count = count - 1 |
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n = n >> 1 |
// shift n right one bit |
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} |
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if count = 0 then output 1
else
output 0
assert done
The functional units required by the custom datapath are as follows:
•A shifter with parallel load register for storing n.
•One 3-bit up/down counter for count.
•A “not equal to 0” comparator and an “equal to 0” comparator.
Customize datapath
Microprocessor Design – Principles and Practices with VHDL |
Last updated 3/18/2003 7:58 PM |
Chapter 11 – Dedicated Microprocessors |
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Page 22 of 25 |
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Input |
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Shift |
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shifter w |
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Load |
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load |
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n ≠ |
0 |
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LSB = 1 |
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Clear |
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up/down |
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E |
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counter |
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count = 0 |
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Out |
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Output |
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Done |
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State-action table for the Moore FSM |
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Current State |
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Next State |
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Unconditional |
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Q3Q2Q1Q0 Name |
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[Condition, State] |
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Control and Datapath Actions |
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0 0 0 0 |
s0 |
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0, s0 |
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count = 0 |
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start = |
1, s |
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done = 0 |
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1 |
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output = Z |
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0 0 0 1 |
s1 |
s2 |
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n = input |
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0 0 1 0 |
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n ≠ |
0, s3 |
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n = |
0, s6 |
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0 0 1 1 |
s3 |
LSB(n) = |
1, s4 |
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1, s5 |
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LSB(n) ≠ |
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0 1 0 0 |
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s2 |
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count = count + 1 |
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n = n >> 1 |
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0 1 0 1 |
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s2 |
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count = count – 1 |
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n = n >> 1 |
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0 1 1 0 |
s6 |
count = |
0, s7 |
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1, s8 |
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count = |
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0 1 1 1 |
s7 |
s0 |
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output = 1 |
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done = 1 |
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1 0 0 0 |
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s0 |
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output = 0 |
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done = 1 |
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We will use D flip-flops to implement the state memory. To derive the next-state equations for the Moore FSM, we can convert the state-action table to a K-map and follow the steps as described in section 6.3?? or we can derive the equations as follows:
The following is done without simplifications of the state encodings.
Next-state equations using D flip-flops, Di = Qi(next) are:
For D0, Q0 = 1 in states s1, s3, s5, and s7, therefore, we look for these states in the next state column, i.e. what is the current state and may be an optional condition that will lead to these states. Hence, we get
D0 = s0(start) + s2(n ≠ 0) + s3(LSB = 1)' + s6(count = 0)
Microprocessor Design – Principles and Practices with VHDL |
Last updated 3/18/2003 7:58 PM |
Chapter 11 – Dedicated Microprocessors |
Page 23 of 25 |
= Q3'Q2'Q1'Q0'(start) + Q3'Q2'Q1Q0' (n ≠ 0) + Q3'Q2'Q1Q0 (LSB = 1)' + Q3'Q2Q1Q0' (count = 0)
D1 = s1 + s4 + s5 + s2(n ≠ 0) + s2(n ≠ 0)' + s6(count = 0)
=s1 + s2 + s4 + s5 + s6(count = 0)
=Q3'Q2'Q1'Q0 + Q3'Q2'Q1Q0' + Q3'Q2Q1'Q0' + Q3'Q2Q1'Q0 + Q3'Q2Q1Q0' (count = 0)
D2 = s3(LSB = 1) + s3(LSB = 1)' + s2(n = 0) + s6(count = 0)
= Q3'Q2'Q1Q0 + Q3'Q2'Q1Q0' (n = 0) + Q3'Q2Q1Q0' (count = 0)
D3 = s6(count = 0)'
= Q3'Q2Q1Q0' (count = 0)'
The output equations are:
Shift = s4 + s5 = Q3'Q2Q1'Q0' + Q3'Q2Q1'Q0
Load = s1 = Q3'Q2'Q1'Q0
Clear = s0 = Q3'Q2'Q1'Q0'
E = s4 + s5 = Q3'Q2Q1'Q0' + Q3'Q2Q1'Q0
Out = s7 + s8 = Q3'Q2Q1Q0 + Q3Q2'Q1'Q0'
The Moore FSM circuit is as follows:
start = 1 |
LSB ≠ |
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n ≠ |
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count = 0 |
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D3 |
Q3 |
Shift |
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Clk |
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Q'3 |
Load |
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Clear |
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D2 |
Q2 |
Out |
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Clk |
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Q'2 |
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D1 |
Q1 |
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Clk |
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Q'1 |
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D0 |
Q0 |
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Clk |
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Q'0 |
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Clock |
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State-action table for the Mealy FSM
Microprocessor Design – Principles and Practices with VHDL |
Last updated 3/18/2003 7:58 PM |
Chapter 11 – Dedicated Microprocessors |
Page 24 of 25 |
Current State |
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Next State |
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Control and Datapath Actions |
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Q1 Q0 |
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0 0 |
s0 |
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count = 0 |
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1, s |
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done = 0 |
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output = Z |
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0 1 |
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n = input |
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1 0 |
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LSB(n) = |
1, count = |
count + |
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1 |
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1, count = |
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count − 1 |
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n >> 1 |
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n ≠ 0, n = |
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1 1 |
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s0 |
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done = 1 |
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count = |
0, output = |
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count ≠ |
0, output = |
0 |
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♦
Microprocessor Design – Principles and Practices with VHDL |
Last updated 3/18/2003 7:58 PM |
Chapter 11 – Dedicated Microprocessors
Index
A
Application specific integrated circuit. See ASIC ASIC, 2
B
Behavioral model, 17
C
Control signal, 2, 3
Control unit, 2, 9
See also Finite-state machine.
Controller. See Control unit
D
Datapath, 2
Dedicated microprocessor, 2
E
Excitation equation, 4
F
Finite-state machine, 2
See also Control unit.
FSM. See Finite-state machine
FSM+D model, 2, 3, 11
FSMD model, 3, 14
G
General-purpose microprocessor, 2
Page 25 of 25
Generating status signal. See Status signal
I
Implementation table, 4, 9
N
Next-state logic, 2, 9
Next-state table, 4, 9
O
Output logic, 2, 9
S
State memory, 2 Status signal, 2, 3, 10
generating, 10
U
Unused state encoding, 9
V
VHDL code
dedicated microprocessor (behavioral) for summation algorithm, 17
dedicated microprocessor (FSM+D) for summation algorithm, 14
dedicated microprocessor (FSMD) for summation algorithm, 16
FSM for summation algorithm, 13
Microprocessor Design – Principles and Practices with VHDL |
Last updated 3/18/2003 7:58 PM |