11.Dedicated microprocessors

Figure 4. Corrected state diagram for the summation algorithm shown in Figure 2(a).

11.2 FSM + D Model Using VHDL

In the previous section, we constructed the microprocessor by manually constructing the FSM and the datapath separately and then join them together. For the FSM, we started from the state diagram. The excitation equations and the output equations were manually derived from the next-state table and the output table respectively. These equations were then used to construct the next-state logic circuit and the output logic circuit in the FSM.

Instead of manually constructing the FSM, an alternative way is to automatically synthesize it from behavioral VHDL code. A separate general or dedicated datapath is still used as before and is described in VHDL. The final dedicated microprocessor is constructed by using an enclosing VHDL entity written at the structural level.

The behavioral VHDL code for the FSM follows the standard method for coding a state machine. There will be two processes – one for the next-state logic and the other for the output logic.

Example 11.2

Figure 5 shows the behavioral VHDL code for the FSM for the summation algorithm of Example 8.3. In the entity section, the output signals include all the control signals for controlling the datapath. The input signals are the status signals from the datapath. In the architecture section, there are two processes, the next-state logic and the output logic that execute concurrently. The main statement within these two processes is the CASE statement that determines what the current state is. For the next-state process, the State signal (variable) is assigned a new state value at the next rising clock edge. The new state value is, of course, dependent on the current state and input signals, if any. In the output process, all control signals are generated for every case, i.e. all the control signals must be assigned a value in every case. Otherwise, VHDL will synthesize these signals to memory elements instead (see Section 6.10.1), and we do not want that.

For the datapath, we are using the same general datapath as discussed in Section 8.5. The VHDL code for this datapath is listed in Figure 8.12 and Figure 8.13. Figure 8.12 describes the individual components used in the datapath and Figure 8.13 combines these components into the desired datapath.

Finally, Figure 6 combines the datapath and the FSM together using VHDL structural level coding style to give the microprocessor top-level entity sum.

The simulation trace is shown in Figure 7 for the input n = 10. After asserting the start signal in state s0, the input value 10 is read in during state s2. The value 10 is written to RF1 at the next rising clock edge, which also brings the FSM to state s3. RF1 is for storing n that counts from 10 down to 0. RF0 is for storing sum and is updated after each count of n. When RF1 reaches zero, the sum 55 from RF0 is sent to the output, and the FSM stays in state s0 waiting for another start signal. ♦

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY fsm IS PORT (

clock, reset, start: IN std_logic; IE: OUT std_logic;

WE: OUT std_logic;

WA: OUT std_logic_vector (1 DOWNTO 0); RAE: OUT std_logic;

RAA: OUT std_logic_vector (1 DOWNTO 0); RBE: OUT std_logic;

RBA: OUT std_logic_vector (1 DOWNTO 0); aluSel : OUT std_logic_vector(2 DOWNTO 0); shSel: OUT std_logic_vector (1 DOWNTO 0); OE: OUT std_logic;

done: OUT std_logic; neq0: IN std_logic);

END fsm;

ARCHITECTURE fsm_arc OF fsm IS

TYPE state_type IS (s0, s1, s2, s3, s4, s5); SIGNAL state: state_type;

BEGIN

next_state_logic: PROCESS(reset, clock) BEGIN

IF(reset = '1') THEN state <= s0;

ELSIF(clock'EVENT AND clock = '1') THEN CASE state IS

WHEN s0 =>

IF(start = '1') THEN state <= s1; ELSE state <= s0; END IF; WHEN s1 =>

state <= s2; WHEN s2 =>

state <= s3; WHEN s3 =>

state <= s4; WHEN s4 =>

IF(neq0 = '1') THEN state <= s3; ELSE state <= s5; END IF; WHEN s5 =>

state <= s0; WHEN OTHERS =>

state <= s0; END CASE;

END IF;

END PROCESS;

output_logic: PROCESS(state) BEGIN

CASE state IS WHEN s1 =>

IE<='0'; WE<='1'; WA<="00"; RAE<='1'; RAA<="00"; RBE<='1'; RBA<="00"; aluSel<="101"; shSel<="00"; OE<='0'; done<='0';

WHEN s2 =>

BEGIN

--doing structural modeling here

--FSM control unit

U0: fsm PORT MAP(clock,reset,start,IE,WE,WA,RAE,RAA,RBE,RBA, aluSel,shSel,OE,done,neq0);

-- Datapath

U1: datapath PORT MAP (clock,input,IE,WE,WA,RAE,RAA,RBE,RBA, aluSel,shSel,OE,output,neq0);

END Structural;

Figure 6. FSM+D microprocessor entity for the summation algorithm. .

Figure 7. Simulation trace of the FSM+D summation algorithm with input n = 10.

11.3 FSMD Model

When writing VHDL code using the FSM+D model, we need to construct both the datapath component and the FSM component. These two components are then joined together at the structural level using the control signals and status signals from the two components. Using this method to build a microprocessor with a large datapath is a lot of work because in addition to building the FSM, we need to first construct the datapath and then we need to connect the numerous control and status signals together. The FSM of course, has to generate all the control signals.

The FSMD (finite-state machine with datapath) model is an abstraction used when we write VHDL code for a microprocessor. Instead of separating the FSM and the datapath entities, we combine the FSM and the datapath together into the same entity. In other words, all the data operations that need to be performed by the datapath are actually imbedded in the FSM coding itself as VHDL data manipulation statements. After all, there are built-in VHDL operators to perform data manipulations. As a result, when writing VHDL code for the FSMD model, we do not need to construct the datapath component at the structural level and, therefore, there are no control and status signals to be connected. Thus, the FSMD model is an abstraction for simplifying the VHDL code for a microprocessor.

Writing VHDL code using the FSM+D model allows a person to have full control as to what components are used in the datapath and how these components are connected to the FSM. Whereas, writing VHDL code using the FSMD model automates the datapath construction process. The synthesizer now decides what components are needed by the datapath. However, since you are still writing the FSM process code manually, you still have full control as to what instructions are executed in what state and how many states there are.

Example 10.3

Figure 8 shows the complete VHDL code using the FSMD model for the summation algorithm of Example 8.3. Notice the simplicity of this code as compare to the code for the FSM+D model shown in the previous section. Here, we have just one entity, which serves as both the top-level microprocessor entity and the FSMD entity. The architecture section is written similar to a regular FSM with the different cases for each of the states. The main difference is that there is no output process. Like before for the next-state process, the CASE statement selects the current state and determines the next state. But in addition to setting the next state, each case (state) also contains data operation statements such as sum = sum + n. This replaces the need for the output process for generating the output signals.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

ENTITY sum IS PORT (

clock, reset, start: IN std_logic; input: IN std_logic_vector(7 DOWNTO 0); done: OUT std_logic;

output: OUT std_logic_vector(7 DOWNTO 0)); END sum;

ARCHITECTURE FSMD OF sum IS

TYPE state_type IS (s0, s1, s2, s3, s4, s5); SIGNAL state: state_type;

BEGIN

next_state_logic: PROCESS(reset, clock) VARIABLE sum: std_logic_vector(7 DOWNTO 0); VARIABLE n: std_logic_vector(7 DOWNTO 0);

BEGIN

IF(reset = '1') THEN state <= s0;

done <= '0';

output <= (others => '0'); ELSIF(clock'EVENT AND clock = '1') THEN

CASE state IS WHEN s0 =>

IF (start = '1') THEN state <= s1; ELSE state <= s0; END IF; sum := (others => '0');

done <= '0';

output <= (others => '0'); WHEN s1 =>

--reading n in the following statement is BEFORE the decrement

--therefore, we need to compare with 1 and not 0

IF (n /= 1) THEN state <= s3; ELSE state <= s5; END IF; n := n - 1;

done <= '0';

output <= (others => '0'); WHEN s5 =>

state <= s0; done <= '1'; output <= sum;

WHEN OTHERS => state <= s0;

END CASE; END IF;

END PROCESS; END FSMD;

Figure 8. VHDL code for the FSMD model of the summation algorithm.

Figure 9. Simulation trace of the FSMD summation algorithm with input n = 10.

11.4 Behavioral Model

The complete microprocessor can also be designed by writing VHDL code in a truly behavioral style so that both the FSM and the datapath are synthesized automatically. Using the behavioral model to design a circuit is quite similar to writing computer programs using a high-level language. The synthesizer, like the compiler, will translate the VHDL behavioral description of the circuit automatically to a netlist. This netlist can then be programmed directly to a FPGA chip.

Chapter 11 – Dedicated Microprocessors Page 17 of 25

Since the synthesizer automatically constructs both the FSM and the datapath, therefore, you have no control over what parts are used in the datapath and what control words are executed in what state of the FSM. Not being able to decide what components are used in the datapath is not too big of a problem because the synthesizer does do a good job in deciding that for you. The issue is with not being able to say what control words are executed in what state of the FSM. This is purely a timing issue. In some timing critical applications such as communication protocols and real-time controls, we need to control exactly in what clock cycle a certain operation is performed. In other words, we need to be able to assign a control word to a specific state of the FSM.

Behavioral VHDL code offers all the basic language constructs that are available in most computer programming languages such as variable assignments, FOR LOOPS and IF-THEN-ELSES. These statements are executed sequentially.

Example 11.4

Figure 10 shows the VHDL code using the behavioral model for the summation algorithm of Example 8.3. Note that some VHDL synthesizers such as MaxPlus+II do not allow the use of loops that cannot be unrolled, i.e. loops with variables for their starting or ending value whose values are unknown at compile time. Hence, in the code, the value for the variable n cannot be from a user input.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY sum IS PORT ( start: IN STD_LOGIC; done: OUT STD_LOGIC; output: OUT INTEGER);

END sum;

ARCHITECTURE Behavioral OF sum IS BEGIN

PROCESS

VARIABLE n: integer; VARIABLE sum: integer;

BEGIN

IF (start = '0') THEN done <= '0'; output <= 0;

ELSE

sum := 0;

n := 10; -- cannot be user input FOR i in n DOWNTO 1 LOOP

sum := sum + i; END LOOP;

done <= '1'; output <= sum;

END IF;

END PROCESS; END Behavioral;

Figure 10. VHDL code for the behavioral model of the summation algorithm.

11.5 Examples

Example 11.5

This is an example for evaluating the GCD (Greatest Common Denominator) of two values.

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.all;

--------------------------------------------------------------

entity GCD is

port( clock: in std_logic; reset: in std_logic; start: in std_logic;

X_input: in unsigned(3 downto 0); Y_input: in unsigned(3 downto 0); output: out unsigned(3 downto 0)

);

end GCD;

--------------------------------------------------------------

if (start='1') then

X:= X_input;

Y:= Y_input; State := S1;

Chapter 11 – Dedicated Microprocessors Page 19 of 25

if (X<Y) then

State := S0; end case;

end if;

end process; end FSMD;

Example 11.6

This is an example for evaluating the factorial of n (n!).

input n product = 1 while n > 1

product = product * n n = n – 1

output product

The following registers and functional units are needed in the datapath:

•One register for variable product.

•One down counter with parallel load for storing variable n and for decrementing n.

•One multiply functional unit.

•One greater-than-one comparator.

Customize datapath

State action table for the Moore FSM

Using D flip-flops and straight binary encoding to construct the above FSM…