08.Sequential components

Figure 13. A 4-bit binary up counter with asynchronous clear: (a) circuit; (b) truth table; (c) logic symbol.

The VHDL code for the 4-bit binary up counter is shown in Figure 14 and the simulation trace in Figure 15.

ENTITY counter IS PORT (

Clock: IN BIT;

Clear: IN BIT;

Count: IN BIT;

Q : OUT INTEGER RANGE 0 TO 15);

END counter;

ARCHITECTURE Behavioral OF counter IS BEGIN

PROCESS (Clock, Clear)

VARIABLE value: INTEGER RANGE 0 TO 15; BEGIN

IF Clear = '1' THEN value := 0;

ELSIF (Clock'EVENT AND Clock='1') THEN IF Count = '1' THEN

value := value + 1; END IF;

END IF;

Q <= value; END PROCESS; END Behavioral;

Figure 14. VHDL code for a 4-bit binary up counter.

Figure 15. Simulation trace for the 4-bit binary up counter.

8.5.2 Binary Up-Down Counter

We can design an n-bit binary up-down counter just like the up counter except that we need both an adder and a subtractor for the data input to the register. The half adder/subtractor (HAS) truth table is shown in Figure 16 (a). The D signal is to select whether we want to count up or down. Asserting D (setting to 1) will count down. The top half of the table is exactly the same as the HA truth table. For the bottom half, we are performing a subtraction of a

– cin. s is the difference of the subtraction and cout is a 1 if we need to borrow. For example, for 0 – 1, we need to borrow, so cout is a 1. When we borrow, we get a 2, and 2 – 1 = 1, so s is also a 1. The two resulting equations are

cout = D' a cin + D a' cin = (D a) cin s = D' (a cin) + D (a cin) = a cin

The circuit and logic symbol for the half adder/subtractor is shown in Figure 16 (b) and (c).

(a)

Figure 16. Half adder/subtractor (HAS): (a) truth table; (b) circuit; (c) logic symbol.

A 4-bit binary up-down counter circuit is shown in Figure 17 (a). Its truth table and logic symbol are shown in

(b) and (c). The VHDL code and the simulation trace are shown in Figure 18 and Figure 19 respectively.

Figure 17. A 4-bit binary up-down counter with asynchronous clear: (a) circuit; (b) truth table; (c) logic symbol.

ENTITY counter IS PORT (

Clock: IN BIT;

Clear: IN BIT;

Count: IN BIT;

Down: IN BIT;

Q: OUT INTEGER RANGE 0 TO 15);

END counter;

Figure 18. VHDL code for a 4-bit binary up-down counter.

Figure 19. Simulation trace for the 4-bit binary up-down counter.

8.5.3 Binary Up-Down Counter with Parallel Load

To make the binary counter more versatile, we need to be able to start the count sequence with any number rather than zero. This is easily accomplished by modifying our counter circuit to allow it to load in an initial value. With the value loaded into the register, we can now count starting from this new value. The modified counter circuit is shown in Figure 20 (a). The only difference between this circuit and that of Figure 17 (a) is that a 2-input multiplexer is added between the s output of the HAS and the Di input of the flip-flop. By doing this, the input of the flip-flop can be selected from either an external input value if Load is asserted or the next count value from the HAS output if Load is de-asserted. If the HAS output is selected, then the circuit works exactly like before. If the external input is selected, then whatever value is presented on the input data lines will be loaded into the register. The operational table and logic symbol for this circuit is shown in Figure 20 (b) and (c).

We have kept the Clear line, so that the counter can still be initialized to zero at anytime. Notice that there is a timing difference between asserting the Clear line to reset the counter to zero as oppose to loading in a zero by asserting the Load line and setting the data input to a zero. In the first case, the counter is reset to zero immediately after the Clear is asserted while the latter case will reset the counter to zero at the next rising edge of the clock.

With this circuit, the count will start with whatever value is loaded into the register. However, when the counter reaches the end of the count sequence, it will cycle back to zero and not to this new value. We can add a simple comparator circuit to this counter so that it will cycle back to this new input value rather than zero as shown in the next section.

8.5.4 BCD Up-Down Counter

The problem with the binary up-down counter with parallel load is that when it reaches the end of the count sequence, it always cycles back to zero. If we want the count sequence to cycle back to the initial loaded value each time, we need to assert the Load at the beginning of each count cycle and the initial value to be loaded still present on the input data lines. To generate an assert signal for the Load line, we need to check the count value to see if it is at the end of the count sequence. If it is, a 1 is outputted to assert the Load. This in turn loads in the initial value and the count continues with this initial value. This circuit is just a comparator circuit with one set of its inputs coming from the register and the other being the constant that you are checking for. The output of the comparator will assert the Load line.

The BCD (binary coded decimal) up-down counter counts from 0 to 9 for the up sequence and the reverse for the down sequence. For the up sequence, when the count reaches 9, we need to assert the Load line and load in a 0. For the down sequence, when the count reaches 0, we need to assert the Load line and load in a 9. The BCD upcounter is shown in Figure 21 (a) and the BCD up-down counter in (b).

Figure 20. A 4-bit up-down binary counter with parallel load and asynchronous clear: (a) circuit; (b) truth table; (c) logic symbol.

Figure 21. BCD counters: (a) up counter; (b) up-down counter.

In the BCD up-down counter, two 5-input AND gates acting as comparators are used. The one label “up” is enabled when Down is a 0 (i.e. counting up) and will output a 1 when the count has reached 9. The one label “dn” will output a 1 when Down is asserted and the count has reached 0. The Down signal is also used as the select to the four multiplexers. The multiplexers work together for loading either a 0 or a 9 into the counter.

8.6Shift Registers

Similar to the combinational shifter and rotator circuits, there are the equivalent sequential shifter and rotator circuits. The circuits for the shift and rotate operations are constructed exactly the same. The only difference in the sequential version is that the operations are performed on the value that is stored in a register. The main usage for a shift register is for converting from a serial data input stream to a parallel data output or vice versa. For a serial to parallel data conversion, the bits are shifted into the register at each clock cycle and when all the bits (usually eight bits) are shifted in, the 8-bit register can be read to produce the eight bit parallel out. For a parallel to serial conversion, the 8-bit register is first loaded with the input data. The bits are then individually shifted out, one bit per clock cycle.

8.6.1 Serial to Parallel Shift Register

Figure 22 shows a 4-bit serial to parallel converter. The input data bits come in from the Data in line. When Shift is asserted, the data bits are shifted in. At the first clock cycle, the first bit gets loaded into Q3. At the second clock cycle, the bit that is in Q3 gets loaded into Q2 while Q3 is loaded with the next bit in the input serial data stream. This continues for four clock cycles until four bits are shifted into the four flip-flops.

The structural VHDL code for a 4-bit serial in parallel out shift register is shown in Figure 23 and the simulation trace in Figure 24.

Figure 22. A 4-bit serial in parallel out shift register circuit.

8.6.2 Serial-to-Parallel and Parallel-to-Serial Shift Register

For both the serial to parallel and parallel to serial operations, we perform the same left to right shifting of bits through the register. The only difference between the two operations is whether we want to perform a parallel read after the shifting or a parallel write before the shifting. For the serial to parallel operation, we want to perform a parallel read after the bits have shifted in. On the other hand, for the a parallel to serial operation we want to perform a parallel write first and then shift the bits out as a serial stream. We can implement both functionalities into the serial to parallel circuit from the previous section simply by adding a parallel load function to the circuit as shown in Figure 25 (a). The four multiplexers work together for selecting whether we want the flip-flops to retain the current value, load in a new value or shift the bits to the right by one bit position. The operation of this circuit is dependent on the two select lines SHSel1 and SHSel0, which controls which input of the multiplexers is selected. The operation table and logic symbol are shown in Figure 25 (b) and (c) respectively. The VHDL code and the simulation trace for this shift register is shown in Figure 26 and Figure 27 respectively.

Figure 25. A 4-bit serial-to-parallel and parallel-to-serial shift register: (a) circuit; (b) operational table; (c) logic symbol.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY shiftreg IS PORT (

Clock: IN STD_LOGIC;

SHSel: IN STD_LOGIC_VECTOR(1 DOWNTO 0);

Serial_in: IN STD_LOGIC;

D: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

Serial_out: OUT STD_LOGIC;

Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END shiftreg;

ARCHITECTURE Behavioral OF shiftreg IS

SIGNAL content: STD_LOGIC_VECTOR(3 DOWNTO 0);

Figure 26. Behavioral VHDL code for a 4-bit serial-to-parallel and parallel-to-serial shift register.

Figure 27. Sample trace for the 4-bit serial-to-parallel and parallel-to-serial shift register.