6.Experiments

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4001

INSTRUCTIONS

The 4001 integrated circuit is a CMOS quad NOR gate, identical in input, output, and power supply pin assignments to the 4011 quad NAND gate. Its "pinout," or "connection," diagram is as such:

"Pinout," or "connection" diagram for the 4001 quad NOR gate

VDD

Gnd

When two NOR gates are cross-connected as shown in the schematic diagram, there will be positive feedback from output to input. That is, the output signal tends to maintain the gate in its last output state. Just as in op-amp circuits, positive feedback creates hysteresis. This tendency for the circuit to remain in its last output state gives it a sort of "memory." In fact, there are solid-state computer memory technologies based on circuitry like this!

If we designate the left switch as the "Set" input and the right switch as the "Reset," the left LED will be the "Q" output and the right LED the "Q-not" output. With the Set input "high" (switch on) and the Reset input "low," Q will go "high" and Q-not will go "low." This is known as the set state of the circuit. Making the Reset input "high" and the Set input "low" reverses the latch circuit's output state: Q "low" and Q-not "high." This is known as the reset state of the circuit. If both inputs are placed into the "low" state, the circuit's Q and Q-not outputs will remain in their last states, "remembering" their prior settings. This is known as the latched state of the circuit.

Because the outputs have been designated "Q" and "Q-not," it is implied that their states will always be complementary (opposite). Thus, if something were to happen that forced both outputs to the same state, we would be inclined to call that mode of the circuit "invalid." This is exactly what will happen if we make both Set and Reset inputs "high:" both Q and Q-not outputs will be forced to the same "low" logic state. This is known as the invalid or illegal state of the circuit, not because something has gone wrong, but because the outputs have failed to meet the expectations established by their labels.

Since the "latched" state is a hysteretic condition whereby the last output states are "remembered," one might wonder what will happen if the circuit powers up this way, with no previous state to hold. To experiment, place both switches in their o® positions, making both Set and Reset inputs low, then disconnect one of the battery wires from the breadboard. Then, quickly make and break contact between that battery wire and its proper connection point on the breadboard, noting the status of the two LEDs as the circuit is powered up again and again:

make and break contact!

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4011

When a latch circuit such as this is powered up into its "latched" state, the gates race against each other for control. Given the "low" inputs, both gates try to output "high" signals. If one of the gates reaches its "high" output state before the other, that "high" state will be fed back to the other gate's input to force its output "low," and the race is won by the faster gate.

Invariably, one gate wins the race, due to internal variations between gates in the chip, and/or external resistances and capacitances that act to delay one gate more than the other. What this usually means is that the circuit tends to power up in the same mode, over and over again. However, if you are persistent in your powering/unpowering cycles, you should see at least a few times where the latch circuit powers up latched in the opposite state from normal.

Race conditions are generally undesirable in any kind of system, as they lead to unpredictable operation. They can be particularly troublesome to locate, as this experiment shows, because of the unpredictability they create. Imagine a scenario, for instance, where one of the two NOR gates was exceptionally slow-acting, due to a defect in the chip. This handicap would cause the other gate to win the power-up race every time. In other words, the circuit will be very predictable on power-up with both inputs "low." However, suppose that the unusual chip were to be replaced by one with more evenly matched gates, or by a chip where the other NOR gate were consistently slower. Normal circuit behavior is not supposed to change when a component is replaced, but if race conditions are present, a change of components may very well do just that.

Due to the inherent race tendency of an S-R latch, one should not design a circuit with the expectation of a consistent power-up state, but rather use external means to "force" the race so that the desired gate always "wins."

An interesting modi¯cation to try in this circuit is to replace one of the 470 - LED "dropping" resistors with a lower-value unit, such as 100 -. The obvious e®ect of this alteration will be increased LED brightness, as more current is allowed through. A not-so-obvious e®ect will also result, and it is this e®ect which holds great learning value. Try replacing one of the 470 - resistors with a 100 - resistor, and operate the input signal switches through all four possible setting combinations, noting the behavior of the circuit.

You should note that the circuit refuses to latch in one of its states (either Set or Reset), but only in the other state, when the input switches are both set "low" (the "latch" mode). Why is this? Take a voltmeter and measure the output voltage of the gate whose output is "high" when both inputs are "low." Note this voltage indication, then set the input switches in such a way that the other state (either Reset or Set) is forced, and measure the output voltage of the other gate when its output is "high." Note the di®erence between the two gate output voltage levels, one gate loaded by an LED with a 470 - resistor, and the other loaded by an LED with a 100 - resistor. The one loaded down by the "heavier" load (100 - resistor) will be much less: so much less that this voltage will not be interpreted by the other NOR gate's input as a "high" signal at all as it is fed back! All logic gates have permissible "high" and "low" input signal voltage ranges, and if the voltage of a digital signal falls outside this permissible range, it might not be properly interpreted by the receiving gate. In a latch circuit such as this, which depends on a solid "high" signal fed back from the output of one gate to the input of the other, a "weak" signal will not be able to maintain the positive feedback necessary to keep the circuit latched in one of its states.

This is one reason I favor the use of a voltmeter as a logic "probe" for determining digital signal levels, rather than an actual logic probe with "high" and "low" lights. A logic probe may not indicate the presence of a "weak" signal, whereas a voltmeter de¯nitely will by means of its quantitative indication. This type of problem, common in circuits where di®erent "families" of integrated circuits are mixed (TTL and CMOS, for example), can only be found with test equipment providing quantitative measurements of signal level.

7.4NAND gate S-R enabled latch

PARTS AND MATERIALS

²4011 quad NAND gate (Radio Shack catalog # 276-2411)

²Eight-position DIP switch (Radio Shack catalog # 275-1301)

²Ten-segment bargraph LED (Radio Shack catalog # 276-081)

²One 6 volt battery

²Three 10 k- resistors

²Two 470 - resistors

Caution! The 4011 IC is CMOS, and therefore sensitive to static electricity!

CROSS-REFERENCES

Lessons In Electric Circuits, Volume 4, chapter 3: "Logic Gates"

Lessons In Electric Circuits, Volume 4, chapter 10: "Multivibrators"

LEARNING OBJECTIVES

² Principle and function of an enabled latch circuit

SCHEMATIC DIAGRAM

ILLUSTRATION

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4011

INSTRUCTIONS

Although this circuit uses NAND gates instead of NOR gates, its behavior is identical to that of the NOR gate S-R latch (a "high" Set input drives Q "high," and a "high" Reset input drives Q-not "high"), except for the presence of a third input: the Enable. The purpose of the Enable input is to enable or disable the Set and Reset inputs from having e®ect over the circuit's output status. When the Enable input is "high," the circuit acts just like the NOR gate S-R latch. When the Enable input is "low," the Set and Reset inputs are disabled and have no e®ect whatsoever on the outputs, leaving the circuit in its latched state.

This kind of latch circuit (also called a gated S-R latch), may be constructed from two NOR gates and two AND gates, but the NAND gate design is easier to build since it makes use of all four gates in a single integrated circuit.

7.5NAND gate S-R °ip-°op

PARTS AND MATERIALS

²4011 quad NAND gate (Radio Shack catalog # 276-2411)

²4001 quad NOR gate (Radio Shack catalog # 276-2401)

²Eight-position DIP switch (Radio Shack catalog # 275-1301)

²Ten-segment bargraph LED (Radio Shack catalog # 276-081)

²One 6 volt battery

²Three 10 k- resistors

²Two 470 - resistors

Caution! The 4011 IC is CMOS, and therefore sensitive to static electricity!

Although the parts list calls for a ten-segment LED unit, the illustration shows two individual LEDs being used instead. This is due to lack of room on my breadboard to mount the switch assembly, two integrated circuits, and the bargraph. If you have room on your breadboard, feel free to use the bargraph as called for in the parts list, and as shown in prior latch circuits.

CROSS-REFERENCES

Lessons In Electric Circuits, Volume 4, chapter 3: "Logic Gates"

Lessons In Electric Circuits, Volume 4, chapter 10: "Multivibrators"

LEARNING OBJECTIVES

²The di®erence between a gated latch and a °ip-°op

²How to build a "pulse detector" circuit

²Learn the e®ects of switch contact "bounce" on digital circuits

SCHEMATIC DIAGRAM

Input

Output

Delayed input

Input

Delayed input

Output

Brief period of time when both inputs of the NOR gate are low

The single NOR gate and three inverter gates create this e®ect by exploiting the propagation delay time of multiple, cascaded gates. In this experiment, I use three NOR gates with paralleled inputs to create three inverters, thus using all four NOR gates of a 4001 integrated circuit:

Pulse detector circuit

Input

1/4 4001 Output

Normally, when using a NOR gate as an inverter, one input would be grounded while the other acts as the inverter input, to minimize input capacitance and increase speed. Here, however, slow response is desired, and so I parallel the NOR inputs to make inverters rather than use the more conventional method.

Please note that this particular pulse detector circuit produces a "high" output pulse at every falling edge of the clock (input) signal. This means that the °ip-°op circuit should be responsive to the Set and Reset input states only when the middle switch is moved from "on" to "o®," not from "o®" to "on."

When you build this circuit, though, you may discover that the outputs respond to Set and Reset input signals during both transitions of the Clock input, not just when it is switched from a "high" state to a "low" state. The reason for this is contact bounce: the e®ect of a mechanical switch rapidly making-and-breaking when its contacts are ¯rst closed, due to the elastic collision of the metal contact pads. Instead of the Clock switch producing a single, clean low-to-high signal transition when closed, there will most likely be several low-high-low "cycles" as the contact pads "bounce" upon o®-to-on actuation. The ¯rst high-to-low transition caused by bouncing will trigger the pulse detector circuit, enabling the S-R latch for that moment in time, making it responsive to the Set and Reset inputs.

Ideally, of course, switches are perfect and bounce-free. In the real world, though, contact bounce is a very common problem for digital gate circuits operated by switch inputs, and must be understood

well if it is to be overcome.