Electrical characteristics |
|
|
STM32F405xx, STM32F407xx |
||||
|
|
|
|
|
|
|
|
|
Table 65. Dynamic characteristics: Ethernet MAC signals for RMII |
|
|||||
|
Symbol |
Rating |
Min |
|
Typ |
Max |
Unit |
|
|
|
|
|
|
|
|
|
tsu(RXD) |
Receive data setup time |
2 |
|
- |
- |
ns |
|
tih(RXD) |
Receive data hold time |
1 |
|
- |
- |
ns |
|
tsu(CRS) |
Carrier sense set-up time |
0.5 |
|
- |
- |
ns |
|
tih(CRS) |
Carrier sense hold time |
2 |
|
- |
- |
ns |
|
td(TXEN) |
Transmit enable valid delay time |
8 |
|
9.5 |
11 |
ns |
|
td(TXD) |
Transmit data valid delay time |
8.5 |
|
10 |
11.5 |
ns |
Table 66 gives the list of Ethernet MAC signals for MII and Figure 48 shows the corresponding timing diagram.
Figure 49. Ethernet MII timing diagram
MII_RX_CLK
MII_RXD[3:0] MII_RX_DV MII_RX_ER
tsu(RXD) |
tih(RXD) |
tsu(ER) |
tih(ER) |
tsu(DV) |
tih(DV) |
MII_TX_CLK
td(TXEN) td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668
Table 66. Dynamic characteristics: Ethernet MAC signals for MII(1)
Symbol |
Parameter |
Min |
Typ |
Max |
Unit |
|
|
|
|
|
|
tsu(RXD) |
Receive data setup time |
9 |
|
- |
|
tih(RXD) |
Receive data hold time |
10 |
|
- |
|
tsu(DV) |
Data valid setup time |
9 |
|
- |
|
tih(DV) |
Data valid hold time |
8 |
|
- |
ns |
tsu(ER) |
Error setup time |
6 |
|
- |
|
|
|
||||
tih(ER) |
Error hold time |
8 |
|
- |
|
td(TXEN) |
Transmit enable valid delay time |
0 |
10 |
14 |
|
td(TXD) |
Transmit data valid delay time |
0 |
10 |
15 |
|
1. Data based on characterization results, not tested in production.
128/185 |
DocID022152 Rev 4 |
STM32F405xx, STM32F407xx |
Electrical characteristics |
|
|
CAN (controller area network) interface
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX).
5.3.2012-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 14.
Table 67. ADC characteristics
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Unit |
||
|
|
|
|
|
|
|
|
|
|
VDDA |
Power supply |
|
1.8(1) |
- |
|
3.6 |
V |
|
VREF+ |
Positive reference voltage |
|
1.8(1)(2)(3) |
- |
VDDA |
V |
|
|
|
|
VDDA = 1.8(1)(3) to |
0.6 |
15 |
|
18 |
MHz |
|
fADC |
ADC clock frequency |
2.4 V |
|
|
|
|
|
|
|
|
VDDA = 2.4 to 3.6 V(3) |
0.6 |
30 |
|
36 |
MHz |
|
(4) |
|
fADC = 30 MHz, |
- |
- |
1764 |
kHz |
|
|
External trigger frequency |
12-bit resolution |
|
|
|
|
|
|
fTRIG |
|
|
|
|
|
|
||
|
|
|
|
- |
- |
|
17 |
1/fADC |
|
V |
Conversion voltage range(5) |
|
0 (VSSA or VREF- |
- |
V |
REF+ |
V |
|
AIN |
|
|
tied to ground) |
|
|
|
|
RAIN(4) |
External input impedance |
See Equation 1 for |
- |
- |
|
50 |
κΩ |
|
details |
|
|||||||
|
|
|
|
|
|
|
|
|
R |
(4)(6) |
Sampling switch resistance |
|
- |
- |
|
6 |
κΩ |
|
ADC |
|
|
|
|
|
|
|
CADC(4) |
Internal sample and hold |
|
- |
4 |
|
- |
pF |
|
capacitor |
|
|
||||||
|
|
|
|
|
|
|
|
|
|
tlat(4) |
Injection trigger conversion |
fADC = 30 MHz |
- |
- |
0.100 |
µs |
|
|
latency |
|
- |
- |
|
(7) |
1/fADC |
|
|
|
|
|
3 |
||||
|
tlatr(4) |
Regular trigger conversion |
fADC = 30 MHz |
- |
- |
0.067 |
µs |
|
|
latency |
|
- |
- |
|
(7) |
1/fADC |
|
|
|
|
|
2 |
||||
|
tS(4) |
Sampling time |
fADC = 30 MHz |
0.100 |
- |
|
16 |
µs |
|
|
3 |
- |
480 |
1/fADC |
|||
|
|
|
|
|||||
tSTAB(4) |
Power-up time |
|
- |
2 |
|
3 |
µs |
|
DocID022152 Rev 4 |
129/185 |
Electrical characteristics |
|
|
STM32F405xx, STM32F407xx |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 67. ADC characteristics (continued) |
|
|
||||
Symbol |
|
|
Parameter |
Conditions |
Min |
|
Typ |
Max |
Unit |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fADC = 30 MHz |
0.50 |
|
- |
16.40 |
µs |
|
|
|
|
|
12-bit resolution |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fADC = 30 MHz |
0.43 |
|
- |
16.34 |
µs |
|
|
|
|
|
10-bit resolution |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
tCONV |
(4) |
Total conversion time (including |
fADC = 30 MHz |
0.37 |
|
- |
16.27 |
µs |
||
|
sampling time) |
8-bit resolution |
|
|||||||
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fADC = 30 MHz |
0.30 |
|
- |
16.20 |
µs |
|
|
|
|
|
6-bit resolution |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
9 to 492 (tS for sampling +n-bit resolution for successive |
1/fADC |
||||
|
|
|
|
|
approximation) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
12-bit resolution |
- |
|
- |
2 |
Msps |
|
|
|
|
|
Single ADC |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Sampling rate |
12-bit resolution |
|
|
|
|
|
||
fS(4) |
Interleave Dual ADC |
- |
|
- |
3.75 |
Msps |
||||
(f |
ADC |
= 30 MHz, and |
|
|||||||
|
|
|
|
|
||||||
|
|
|
|
mode |
|
|
|
|
|
|
|
|
tS = 3 ADC cycles) |
|
|
|
|
|
|
||
|
|
12-bit resolution |
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Interleave Triple ADC |
- |
|
- |
6 |
Msps |
|
|
|
|
|
mode |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
IVREF+(4) |
ADC VREF DC current |
|
|
|
|
|
|
|||
consumption in conversion |
|
- |
|
300 |
500 |
µA |
||||
|
|
mode |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
IVDDA(4) |
ADC VDDA DC current |
|
|
|
|
|
|
|||
consumption in conversion |
|
- |
|
1.6 |
1.8 |
mA |
||||
|
|
mode |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1.VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF).
2.It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V.
3.VDDA -VREF+ < 1.2 V.
4.Based on characterization, not tested in production.
5.VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
6.RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V.
7.For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67.
Equation 1: RAIN max formula
RAIN = |
(k – 0.5) |
– RADC |
|
f--ADC------------×----C-------ADC-----------×----ln----(----2----N---+----2---) |
|||
|
|
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register.
130/185 |
DocID022152 Rev 4 |
STM32F405xx, STM32F407xx |
Electrical characteristics |
|
|
a
Table 68. ADC accuracy at fADC = 30 MHz(1)
Symbol |
Parameter |
Test conditions |
Typ |
Max(2) |
Unit |
ET |
Total unadjusted error |
|
±2 |
±5 |
|
|
|
|
|
|
|
EO |
Offset error |
fPCLK2 = 60 MHz, |
±1.5 |
±2.5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
EG |
Gain error |
fADC = 30 MHz, RAIN < 10 kΩ, |
±1.5 |
±3 |
LSB |
|
|
VDDA = 1.8(3) to 3.6 V |
|
|
|
ED |
Differential linearity error |
±1 |
±2 |
|
|
EL |
Integral linearity error |
|
±1.5 |
±3 |
|
|
|
|
|
|
|
1.Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2.Based on characterization, not tested in production.
3.VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF).
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.16 does not affect the ADC accuracy.
Figure 50. ADC accuracy characteristics
|
[1LSB IDEAL= |
VREF+ |
(or |
VDDA |
depending on package)] |
|
||||
|
4096 |
|
4096 |
|
||||||
|
|
|
|
|
|
|
EG |
|
||
4095 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
4094 |
|
|
|
|
|
|
|
|
|
|
4093 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(2) |
|
|
7 |
|
|
|
|
|
ET |
(3) |
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
(1) |
|
|
6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
5 |
EO |
|
|
|
|
|
EL |
|
|
|
4 |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
3 |
|
|
|
|
|
|
|
ED |
|
|
2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1L SBIDEAL |
|
|
|
||
1 |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
0 |
1 |
2 |
3 |
456 |
|
7 |
4093 |
4094 4095 |
4096 |
|
|
|
|||||||||
VSSA |
|
|
|
|
|
|
|
|
VDDA |
|
ai14395c
1.See also Table 68.
2.Example of an actual transfer curve.
3.Ideal transfer curve.
4.End point correlation line.
5.ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one.
DocID022152 Rev 4 |
131/185 |