Задание
Спроектировать
управляющий цифровой автомат,
функционирующий согласно данной ГСА:
Абстрактный синтез
Q0 Z2 Q1 Q2 Q3 Q4 Q5 Q6 Z3 Z1 Q7 Q9 Q8 Z4
В
случае автомата Мура, каждому состоянию
соответствует определенный выходной
сигнал, следовательно ГСА будет выглядеть
следующим образом:
Таким образом, граф переходов данного автомата будет выглядеть следующим образом:
Q0 W0
Q1 W1
Q5 W5
Q6 W6
Q9 W9
- -
Q8 W8
-
¬Z1 Z4 ¬Z4
Q2 W2
Z1
Q7 W7
- - ¬Z2
Q3 W3
Q4 W4
Z2 Z3
-
¬Z3
Структурный синтез
Т.к. в каждый момент для выбора следующего состояния нам необходим только один из сигналов Z, при помощи дешифратора произведем выборку одного из Z в зависимости от текущего состояния.
Карты Карно для d1, d2, d3, d4
VHDL-код
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-------------------------------------------------------------------
entity ID3 is
port ( A0,A1,A2,A3 : in bit;
O0,O1,O2,O3,O4,O5,O6,O7,O8,O9,O10,O11,O12,O13,O14,O15 : out bit);
end ID3;
-------------------------------------------------------------------
architecture arc of ID3 is
constant Delay : Time := 36 ns;
begin
process(A0, A1, A2, A3)
begin
if (A0='0') and (A1='0') and (A2='0') and (A3='0') then--0
O0<='0' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='0') and (A1='0') and (A2='0') and (A3='1') then--1
O0<='1' after Delay;
O1<='0' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='0') and (A1='0') and (A2='1') and (A3='0') then--2
O0<='1' after Delay;
O1<='1' after Delay;
O2<='0' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='0') and (A1='0') and (A2='1') and (A3='1') then--3
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='0' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='0') and (A1='1') and (A2='0') and (A3='0') then--4
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='0' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
else if (A0='0') and (A1='1') and (A2='0') and (A3='1') then--5
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='0' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='0') and (A1='1') and (A2='1') and (A3='0') then--6
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='0' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='0') and (A1='1') and (A2='1') and (A3='1') then--7
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='0' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='1') and (A1='0') and (A2='0') and (A3='0') then--8
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='0' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='1') and (A1='0') and (A2='0') and (A3='1') then--9
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='0' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='1') and (A1='0') and (A2='1') and (A3='0') then--10
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='0' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='1') and (A1='0') and (A2='1') and (A3='1') then--11
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='0' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='1') and (A1='1') and (A2='0') and (A3='0') then--12
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='0' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='1') and (A1='1') and (A2='0') and (A3='1') then--13
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='0' after Delay;
O14<='1' after Delay;
O15<='1' after Delay;
else if (A0='1') and (A1='1') and (A2='1') and (A3='0') then--14
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='0' after Delay;
O15<='1' after Delay;
else if (A0='1') and (A1='1') and (A2='1') and (A3='1') then--15
O0<='1' after Delay;
O1<='1' after Delay;
O2<='1' after Delay;
O3<='1' after Delay;
O4<='1' after Delay;
O5<='1' after Delay;
O6<='1' after Delay;
O7<='1' after Delay;
O8<='1' after Delay;
O9<='1' after Delay;
O10<='1' after Delay;
O11<='1' after Delay;
O12<='1' after Delay;
O13<='1' after Delay;
O14<='1' after Delay;
O15<='0' after Delay;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
end arc;
-------------------------------------------------------------------
entity LA3 is
port ( I11,I12,I21,I22,I31,I32,I41,I42 : in bit;
O1,O2,O3,O4 : out bit);
end LA3;
-------------------------------------------------------------------
architecture arc of LA3 is
constant DelayOn : Time := 15 ns;
constant DelayOff : Time := 22 ns;
begin
process(I11,I12)
begin
if (I11='1') and (I12='1') then
O1<='0' after DelayOff;
else
O1<='1' after DelayOn;
end if;
end process;
process(I21,I22)
begin
if (I21='1') and (I22='1') then
O2<='0' after DelayOff;
else
O2<='1' after DelayOn;
end if;
end process;
process(I31,I32)
begin
if (I31='1') and (I32='1') then
O3<='0' after DelayOff;
else
O3<='1' after DelayOn;
end if;
end process;
process(I41,I42)
begin
if (I41='1') and (I42='1') then
O4<='0' after DelayOff;
else
O4<='1' after DelayOn;
end if;
end process;
end arc;
-------------------------------------------------------------------
entity LA4 is
port ( I11,I12,I13,I21,I22,I23,I31,I32,I33 : in bit;
O1,O2,O3 : out bit);
end LA4;
-------------------------------------------------------------------
architecture arc of LA4 is
constant DelayOn : Time := 15 ns;
constant DelayOff : Time := 22 ns;
begin
process(I11,I12,I13)
begin
if (I11='1') and (I12='1') and (I13='1') then
O1<='0' after DelayOff;
else
O1<='1' after DelayOn;
end if;
end process;
process(I21,I22,I23)
begin
if (I21='1') and (I22='1') and (I23='1') then
O2<='0' after DelayOff;
else
O2<='1' after DelayOn;
end if;
end process;
process(I31,I32,I33)
begin
if (I31='1') and (I32='1') and (I33='1') then
O3<='0' after DelayOff;
else
O3<='1' after DelayOn;
end if;
end process;
end arc;
-------------------------------------------------------------------
entity LA1 is
port ( I11,I12,I13,I14,I21,I22,I23,I24 : in bit;
O1,O2 : out bit);
end LA1;
-------------------------------------------------------------------
architecture arc of LA1 is
constant DelayOn : Time := 15 ns;
constant DelayOff : Time := 22 ns;
begin
process(I11,I12,I13,I14)
begin
if (I11='1') and (I12='1') and (I13='1') and (I14='1') then
O1<='0' after DelayOff;
else
O1<='1' after DelayOn;
end if;
end process;
process(I21,I22,I23,I24)
begin
if (I21='1') and (I22='1') and (I23='1') and (I24='1') then
O2<='0' after DelayOff;
else
O2<='1' after DelayOn;
end if;
end process;
end arc;
-------------------------------------------------------------------
entity LE1 is
port ( I11,I12,I21,I22,I31,I32,I41,I42 : in bit;
O1,O2,O3,O4 : out bit);
end LE1;
-------------------------------------------------------------------
architecture arc of LE1 is
constant DelayOn : Time := 15 ns;
constant DelayOff : Time := 22 ns;
begin
process(I11,I12)
begin
if (I11='1') or (I12='1') then
O1<='0' after DelayOff;
else
O1<='1' after DelayOn;
end if;
end process;
process(I21,I22)
begin
if (I21='1') or (I22='1') then
O2<='0' after DelayOff;
else
O2<='1' after DelayOn;
end if;
end process;
process(I31,I32)
begin
if (I31='1') or (I32='1') then
O3<='0' after DelayOff;
else
O3<='1' after DelayOn;
end if;
end process;
process(I41,I42)
begin
if (I41='1') or (I42='1') then
O4<='0' after DelayOff;
else
O4<='1' after DelayOn;
end if;
end process;
end arc;
-------------------------------------------------------------------
entity LE3 is
port ( I11,I12,I13,I14,I21,I22,I23,I24,E1,E2 : in bit;
O1,O2 : out bit);
end LE3;
-------------------------------------------------------------------
architecture arc of LE3 is
constant DelayOn : Time := 15 ns;
constant DelayOff : Time := 22 ns;
begin
process(I11,I12,I13,I14,E1)
begin
if ((I11='1') or (I12='1') or (I13='1') or (I14='1')) and (E1='1') then
O1<='0' after DelayOff;
else
O1<='1' after DelayOn;
end if;
end process;
process(I21,I22,I23,I24,E2)
begin
if ((I21='1') or (I22='1') or (I23='1') or (I24='1')) and (E2='1') then
O2<='0' after DelayOff;
else
O2<='1' after DelayOn;
end if;
end process;
end arc;
-------------------------------------------------------------------
entity TM7 is
port ( D1,D2,D3,D4,C12,C34 : in bit;
Q1,nQ1,Q2,nQ2,Q3,nQ3,Q4,nQ4 : out bit);
end TM7;
-------------------------------------------------------------------
architecture arc of TM7 is
constant Delay : Time := 28 ns;
signal Q11,Q22,Q33,Q44 : bit;
begin
process (C12)
begin
if (C12'event) and (C12='0') then
Q11<=D1 after Delay;
Q22<=D2 after Delay;
end if;
end process;
process (C34)
begin
if (C34'event) and (C34='0') then
Q33<=D3 after Delay;
Q44<=D4 after Delay;
end if;
end process;
Q1<=Q11;
Q2<=Q22;
Q3<=Q33;
Q4<=Q44;
nQ1 <= not Q11;
nQ2 <= not Q22;
nQ3 <= not Q33;
nQ4 <= not Q44;
end arc;
-------------------------------------------------------------------
entity LN1 is
port (I1,I2,I3,I4,I5,I6 : in bit;
O1,O2,O3,O4,O5,O6 : out bit);
end LN1;
-------------------------------------------------------------------
architecture arc of LN1 is
constant DelayOn : Time := 15 ns;
constant DelayOff : Time := 22 ns;
begin
process (I1)
begin
if (I1='0') then
O1<= not I1 after DelayOn;
else
O1<= not I1 after DelayOff;
end if;
end process;
process (I2)
begin
if (I2='0') then
O2<= not I2 after DelayOn;
else
O2<= not I2 after DelayOff;
end if;
end process;
process (I3)
begin
if (I3='0') then
O3<= not I3 after DelayOn;
else
O3<= not I3 after DelayOff;
end if;
end process;
process (I4)
begin
if (I4='0') then
O4<= not I4 after DelayOn;
else
O4<= not I4 after DelayOff;
end if;
end process;
process (I5)
begin
if (I5='0') then
O5<= not I5 after DelayOn;
else
O5<= not I5 after DelayOff;
end if;
end process;
process (I6)
begin
if (I6='0') then
O6<= not I6 after DelayOn;
else
O6<= not I6 after DelayOff;
end if;
end process;
end arc;
-------------------------------------------------------------------
entity LL1 is
port ( I11,I12,I21,I22,I31,I32,I41,I42 : in bit;
O1,O2,O3,O4 : out bit);
end LL1;
-------------------------------------------------------------------
architecture arc of LL1 is
constant DelayOn : Time := 15 ns;
constant DelayOff : Time := 22 ns;
begin
process(I11,I12)
begin
if (I11='1') or (I12='1') then
O1<='1' after DelayOff;
else
O1<='0' after DelayOn;
end if;
end process;
process(I21,I22)
begin
if (I21='1') or (I22='1') then
O2<='1' after DelayOff;
else
O2<='0' after DelayOn;
end if;
end process;
process(I31,I32)
begin
if (I31='1') or (I32='1') then
O3<='1' after DelayOff;
else
O3<='0' after DelayOn;
end if;
end process;
process(I41,I42)
begin
if (I41='1') or (I42='1') then
O4<='1' after DelayOff;
else
O4<='0' after DelayOn;
end if;
end process;
end arc;
-------------------------------------------------------------------
entity circuit is
port ( z1,z2,z3,z4,CLK :in bit;
y1,y2,y3,y4: out bit);
end circuit;
-------------------------------------------------------------------
architecture arc of circuit is
component ID3 is
port ( A0,A1,A2,A3 : in bit;
O0,O1,O2,O3,O4,O5,O6,O7,O8,O9,O10,O11,O12,O13,O14,O15 : out bit);
end component;
component LA3 is
port ( I11,I12,I21,I22,I31,I32,I41,I42 : in bit;
O1,O2,O3,O4 : out bit);
end component;
component LA4 is
port ( I11,I12,I13,I21,I22,I23,I31,I32,I33 : in bit;
O1,O2,O3 : out bit);
end component;
component LA1 is
port ( I11,I12,I13,I14,I21,I22,I23,I24 : in bit;
O1,O2 : out bit);
end component;
component TM7 is
port ( D1,D2,D3,D4,C12,C34 : in bit;
Q1,nQ1,Q2,nQ2,Q3,nQ3,Q4,nQ4 : out bit);
end component;
component LE1 is
port ( I11,I12,I21,I22,I31,I32,I41,I42 : in bit;
O1,O2,O3,O4 : out bit);
end component;
component LE3 is
port ( I11,I12,I13,I14,I21,I22,I23,I24,E1,E2 : in bit;
O1,O2 : out bit);
end component;
component LN1 is
port (I1,I2,I3,I4,I5,I6 : in bit;
O1,O2,O3,O4,O5,O6 : out bit);
end component;
component LL1 is
port ( I11,I12,I21,I22,I31,I32,I41,I42 : in bit;
O1,O2,O3,O4 : out bit);
end component;
signal O0,O1,O2,O3,O4,O5,O6,O7,O8,O9,O10,O11,O12,O13,O14,O15 : bit;
signal iz1,iz2,iz3,iz4,z,nz : bit;
signal emo1,emo2,emo3,emo4,emo5,emo6,emo7,emo8 : bit;
signal D1,D2,D3,D4, D21,D2241,D23, D31,D32,D33, D42,D43,D44,D45,D46,D4p1,D4p2 : bit;
signal Q1,nQ1,Q2,nQ2,Q3,nQ3,Q4,nQ4 :bit;
begin
mem : TM7 port map (D1,D2,D3,D4,CLK,CLK,Q1,nQ1,Q2,nQ2,Q3,nQ3,Q4,nQ4);
des : ID3 port map (Q1,Q2,Q3,Q4,O0,O1,O2,O3,O4,O5,O6,O7,O8,O9,O10,O11,O12,O13,O14,O15);
ilin24 : LE1 port map (O0,z1,O3,z2,O5,z3,O7,z4,iz1,iz2,iz3,iz4);
ilin42 : LE3 port map (iz1,iz2,iz3,iz4,nQ2,nQ3,nQ4,'0','1','1',z,D1);
i42 : LA1 port map (Q2,nQ3,Q4,z, nQ1,nQ2,nQ4,z, D32,D33);
i331 : LA4 port map (nQ1,nQ4,nz, Q2,Q3,z, nQ2,Q3,nz, D43,D44,D45);
i332 : LA4 port map (D31,D32,D33, D21,D2241,D23, nQ2,Q3,Q4, D3,D2,D23);
i333 : LA4 port map (D43,D44,D45, D2241,D42,D46, Q2,nQ3,nz, D4p1,D4p2,D46);
i24 : LA3 port map (Q2,nQ3, Q2,nQ4, Q3,nQ4, Q3,nQ4, D21,D2241,D42,D31);
not6 : LN1 port map (z,'1','1','1','1','1',nz,emo1,emo2,emo3,emo4,emo5);
ili24 : LL1 port map (D4p1,D4p2, '1','1', '1','1', '1','1', D4,emo6,emo7,emo8);
y1<=Q1;
y2<=Q2;
y3<=Q3;
y4<=Q4;
end arc;
-------------------------------------------------------------------
entity test1 is
end test1;
-------------------------------------------------------------------
architecture arc1 of test1 is
component circuit is
port ( z1,z2,z3,z4,CLK :in bit;
y1,y2,y3,y4: out bit);
end component;
signal CLK,y1,y2,y3,y4 :bit;
begin
Avtomat : circuit port map('0','0','0','0',CLK,y1,y2,y3,y4);
process
begin
wait for 500 ns;
for i in 0 to 10000 loop
CLK <= '0';
wait for 150 ns;
CLK <= '1';
wait for 150 ns;
end loop;
end process;
end arc1;