“Digital Systems Testing and Design for Testability ”

Prof. Dr. V.N.Yarmolik

Lecture course: 32 hours lectures, 32 hours lab. works

3. Design for Testability

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3.Design for Testability of Digital Circuits

3.1.Practical Rules

Ad Hoc Logic Techniques for testability enhancement

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3.Design for Testability of Digital Circuits

3.1.Practical Rules

Rule #1. To maximize the controllability and observability of the digital circuit

A high controllability is achieved due to the fact that any circuit’s node can be easily set to any desired level (0 or 1). High observability is achieved when the state of any node in the circuit can be easily defined by its external nodes.

To improve the control and observation features of the circuit under test the following methods may be used:

1.Extra Gates Incorporation to improve Testability Measure

2.Extra Input\Output Pins Implementation for the Test Purpose Only

3.Logic and Mechanical adapter application to get the access to uncontrolled internal circuit’s feedback loops.

External input

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3.Design for Testability of Digital Circuits

3.1.Practical Rules

Rule #2. Delete or minimize logical redundancy

IN1 Y

\not\

U0 - AND gate; U1 – NOT gate; OR – gate.

The input node IN2 of the Gate 2AND (U0) is the redundant node. Due to this redundancy Stack-at 1 at this node is not detected by any input patterns.

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3.Design for Testability of Digital Circuits

3.1.Practical Rules

The fault at the redundant node may mask the fault at the another node. The following example shows that the fault stuck-at 1 at the third input (IN3) of the gate U4 is undetectable due to the redundancy, as well as the fault stuck-at 0 at the second input (IN2) of the gate U3 is detectable by the pattern x1x2x3=110. In a case when the faults for the gates U3 and U4 are present both the above mention test does not detect the fault for the gate U3.

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3.Design for Testability of Digital Circuits

3.1.Practical Rules

Rule #3. To provide breaking feedback loops.

Uncontrollable feedback loops are the source of some problems at test generation and fault simulation.

& & &

Combinational logic may not have a feedback loop unless the feedback loop goes via a flip-flop.

Rule #4. Non-three-state driver.

If a signal is driven by more than one driver, the drivers must be of the three- state-type.

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3.Design for Testability of Digital Circuits

3.1Practical Rules

Rule #5. All unused inputs of the gates must be connected to the appropriate points (Power supply or ground)

Rule #6. Complex digital circuits should be partitioning into smaller subcircuits to reduce the test generation complexity.

The test generation complexity for deterministic methods can be approximate by the equation:

Cdeterm. Alg. = k2L3

And for the random search approach:

CRandom Search = k1L2;

Rule #7. The digital and analogue modules in the system must be kept physically apart. This rule may be explained by the fact that the strategy of analogue circuit testing is substantially different from that for testing and diagnosing digital circuits.

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3.Design for Testability of Digital Circuits

3.1.Practical Rules

Rule #8. All clocks used in a circuit design must be controllable and testable by external inputs and outputs of the circuit.

Rule #9. The clock may not be connected, either directly or via combinational logic, to the d-input of the internal flip-flops.

Rule #10. It must be possible to control the asynchronous reset for all the internal flip-flops from an input on the circuit.

Rule # … .

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3.Design for Testability of Digital Circuits

3.1.Testable VHDL code

Combinational feedback loops.

ATPG does not normally support asynchronous design. This means that combinational feedback loops are not permissible.

Example: Suppose that we synthesize the following VHDL code d<=d+a; A signal d is on both sides of the assignment symbol (<=), a combinational feedback loop is obtained. The solution is to break the combinational feedback loop with a flip-flop. The VHDL code can then be written as follows:

q<=q_loop + a;