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“Digital Systems Testing and Design for Testability”

Prof. Dr. V.N.Yarmolik

Lecture course: 48 hours lectures, 32 hours lab. works

5. Self-Testing VLSI Design

5.Self-Testing VLSI Design

5.1. Definitions

Built-In Self-Test (BIST) [Built-In Test, Self-test, Autonomous Test or

Self-Verification], means the capability of a chip, board, or system to test itself. The goal of Built-In Self-Test is to add devices to a design that will allow it to test itself.

Built-In-Test Equipment (BITE). The hardware/software incorporated into a unit to provide DFT or BIST.

On-Line BIST. BIST in which testing occurs during normal operation. Concurrent.

Concurrent On-line BIST. A form of on-line BIST in which testing occurs simultaneously with the normal function.

Off-Line BIST. A form of on-line BIST where testing is carried out while the system is not in its normal operation.

Functional Off-Line BIST. Off-line BIST that uses tests based on the functional description of the circuit-under-test.

Structural Off-line BIST. Off-line BIST that uses tests based on the structure of the circuit-under-test.

5.Self-Testing VLSI Design

5.1.Circuit Structures for BIST

Several schemes for incorporating BIST techniques into a design have been proposed. They fall naturally into four classes:

those that assume no special structure to the circuit under test; those that make use of scan paths in the circuit under test;

those that use the concurrent checking (implicit) circuitry of the design.

BIST Structure for Circuit without Scan Paths.

Normal

Inputs

MUX

Circuit

Normal

Outputs

LFSR

Under

Test

MUX

Pass/Fail

5.Self-Testing VLSI Design

5.1.Circuit Structures for BIST BIST Structure for Circuit without Scan Paths. Intel 80-386

PLA1

PLA2

L	19		12	M	L	12		37	M
F		PLA3		M	F		ROM		M
F		PLA3		I	F		ROM		I
S				S	S				S
R				R	R				R
CU		Ref. S							1
		32	32	1					1
					1		16


RG		ALU				SA	SA
RG		ALU		1					1
				1		SA	SA		1
						SA	SA		4

5.Self-Testing VLSI Design

5.1.Circuit Structures for BIST

BILBO Testing

	B	CC1	B	CC2
	I		I
	L		L
	B		B
	O		O
1 Test Session	PRPG		MISR
2 Test Session	MISR		PRPG

B	CC1	B	CC2
I		I
L		L
B		B
O		O
PRPG and		MISR and
MISR		PRPG

These figures show how replacing the two registers in this design with BILBOs will facilitate testing.

5.Self-Testing VLSI Design

5.1.Circuit Structures for BIST BIST Case Study – TMS32010 Data Path

	R1a	R1b
	8	8
	Multiplier
		16
	R2
	16	16
6
Control	ALU	PRPG
Inputs	16
	16
	R3

PRPG		PRPG
R1a		R1b
8		8
Multiplier
		16
PRPG	R2	MISR
PRPG	R2	PRPG
		PRPG
16		16
6
ALU
	16
R3

This is a case study in the literature which describes various configuration of BIST for a section of the TMS32010 data path shown here.

MISR

	BILBO Scheme	6
	2 test session required	6
	2 test session required

5.Self-Testing VLSI Design

5.1.Circuit Structures for BIST BIST Case Study – TMS32010 Data Path

	PRPG	PRPG
	R1a	R1b
	8	8
	Multiplier
		16
	PRPG	R2
	16	16
	6
PRPG	ALU
	ALU
		16
	R3

MISR

Single Signature Testing Scheme

1 test session required

PRPG PRPG

R1a R1b

Multiplier

Extended R2

MISR

16	16
6
ALU
16
R3	MISR

	MISR Scheme 1	7
	1 test session required	7
	1 test session required

5.Self-Testing VLSI Design

5.1.Circuit Structures for BIST BIST Case Study – TMS32010 Data Path

	PRPG	PRPG		This table show the results of the
	R1a	R1b	various schemes. Twenty different runs with
	8	8	different seeds for the PSRGs were done. For
	Multiplier		designs 1, 3, and 4, the simulation was
		16	stopped when fault coverage reached 100%.
	R2	MISR	For design 2, fault coverage saturated at
			64.5%.
	16	16			Single
	6					MISR	MISR
			No. of test	BILBO	signatu
PRPG	ALU					Scheme	Scheme
			patterns	Scheme	re

					testing	I	II

	16		Average	2,177	>3,000	1,457	1,378

	R3	MISR	Minimum	830	-	634	721
			Maximum	3,619	-	2,531	2,121
	MISR Scheme 2		Fault	100%	64.5%	100%	8100%
	1 test session required
			Coverage

5.Self-Testing VLSI Design

5.1.Self-Testing of VLSI with Scan path

Self-Testing based on Scan Path and Signature Analysis. S3 –Technology

...

Inputs

...

PRPG

Input RG

...

	CC1
	...
Internal RG
	...
	CC2
...	...

A S3-technique modification it the LOCST that have been design by IBM for LSSD circuit. Compare to S3 –technique, the main difference of LOCST is that extra storage elements have been introduced in the VLSI design to create PRPG and MISR.

Output RG		MISR
Output RG		MISR
	...		...	9
	Outputs			9
	Outputs

5.Self-Testing VLSI Design

5.1.Self-Testing of VLSI with Scan path

STUMPS Architecture

Pha-

Scan chain

Shi-

Scan chain

fter

Scan chain

CUT

Test Control

Fault coverage based on this

Marchitecture can be reached 95-96%.

	I	For improving the fault
	S	For improving the fault
	S	coverage the additional test point have
	R	coverage the additional test point have
	R	to be added, as well as deterministic
		test patterns generated by ATPG.

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