“Digital Systems Testing and Design for Testability”

Prof. Dr. V.N.Yarmolik

Lecture course: 32 hours lectures, 32 hours lab. works

7. Parametric Testing

(IDDQ Testing)

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7. Parametric Testing

7.1.IDDQ Testing

Efficient test techniques have recently been developed that provide visibility, either virtually or directly, at the logic or even electrical level, which ensure massive observability in a circuit-under-test. Such techniques are referred to as internal access

test methods. Internal access test methods available today include: Iddq, Cross-Checks, Electron Beams, Bed-of Nails and Guided Probe testing. All of this techniques guarantee a good testability for circuits with a good controllability.

With Iddq techniques, observation is at the power supply current terminal that is connected to each of macro cells. Therefore an increase in Iddq indicates the presence of a defect in the macro cells for a given test pattern. This is the main advantage of Iddq testing which allows to get “automatic observability” This results in rapid fault simulation and grading, because only fault sensitization and not propagation is necessary.

On another hand Iddq testing is slow. Typically, less than 1,000 test patterns for Iddq testing can be applied. Thus, the problem of generation of short (minimal) tests is very important for Iddq testing.

supply current (Idd) (quiescent) (ток питания (Idd) (в

7.Parametric Testing

7.1.IDDQ Testing

It has been shown that Iddq testing is an effective method to detect physical defects in CMOS circuits. Physical defects which cause an increased Iddq as for example shorts can be modeled as leakage faults. Realistic leakage fault encompasses gate level bridging faults as well as intra-gate shorts.

Vdd

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Vss

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7.Parametric Testing

7.1.IDDQ Testing

Test Matrix

For the Iddq test with T test patterns for a circuit under test with m inputs and N nodes we denote by Hi the (T m) input test matrix, where rows of Hi are test

patterns and by H the (T N) test matrix, where ith row of H represents logical values at all nodes of the circuit for ith test pattern (i=1,2,…,T).

All BFs in the circuit under test are detectable iff all column in a test matrix, H are different and not equal to all zeros, where a row in H represents an input test pattern and the responses at internal and output nodes.

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From the fact that all column in a test matrix, H are different and not equal to all zeros, we have the following bounds for a number of rows in a test matrix, H which determines the Iddq test complexity. The Iddq test complexity T for detecting all BFs for nonredundunt circuit with m inputs, p internal and n output nodes, satisfies the following inequalities

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7.Parametric Testing

7.1.IDDQ Test Generation

Algorithm #1

Derive the test for the single stuck-at faults and use it as Iddq test.

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7.Parametric Testing

7.1.IDDQ Test Generation

Algorithm #2

Input: Circuit with m inputs, p internal and n output nodes.

1.Derive the value of

qlog2(m 2) ,

2.Generate q rows of test matrix H with the different first n columns which are not equal to all zero and all ones rows.

3.For two equal columns hi and hj (if any) out of matrix H a new row have to be added into the matrix H with the condition that fi fj=1. Where fi corresponds to hi and fj to hj

4.Repeat step #3 for the next two equals column, if there are not equals column go to the step #5.

5.If there is all zero (all ones) column hi within the matrix H, additional row have to be added with the condition fi =1 (fi =0).

Output: Iddq test

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1.q log2(m 2) log2(3 2) 3.

2.Generate 3 rows for the matrix H with the different columns.

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