ЦОС_Заочники2013 / Курсовая МПиЦОС 2011 / Справочная информация / TI / TMS 320 / GLOSSARY
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DSP Glossary
W
wait and signal: See semaphore.
waiting: A state in which a task has voluntarily blocked itself from further execution until an awaited event occurs. The kernel allows a task to wait either for the arrival of a message at a port or for the arrival of a signal at a semaphore.
WAITING state: See task state.
wait queue: A queue of tasks waiting at a port for messages or waiting at a semaphore for signals.
wait state: A period of time that the CPU must wait for external program, data, or I/O memory to respond when reading from or writing to that external memory. The CPU waits one extra cycle for every wait state.
wait-state control register (CWSR): A memory-mapped register that controls the mapping of the program/data wait-state register (PDWSR), the input/output port wait-state register (IOWSR), and the number of wait states. At reset, CWSR = 011112.
wait-state generator: An on-chip peripheral that generates a limited number of wait states for a given off-chip memory space (program, data, or I/O). Wait states are set in the wait-state generator control register (WSGR). (TMS320C2xx, TMS320C24x)
wait-state generator-control register (WSGR): A register that is mapped to I/O memory to control the wait-state generator. (TMS320C2xx, TMS320C24x)
warm boot: The method by which the processor transfers control to the entry address of a previously-loaded program.
WATCH window: A window that displays the values of selected expressions, symbols, addresses, and registers.
WE: See write enable (WE) pin.
well-defined expression: An expression that contains only symbols or assembly-time constants that are defined before they appear in the expression.
window: A defined rectangular area of virtual space on the display.
word: A character or bit string considered as an entity.
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DSP Glossary
write enable (WE) pin: The DSP asserts WE to request a write to external program, data, or I/O space.
WSGR: See wait-state generator control register.
WWW:World Wide Web.
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DSP Glossary
X
XA0±XA13: External address pins for data/program memory or I/O devices. These pins are on the expansion bus of the 'C30. See also A0±An. (TMS320C30)
xba: The assembler keyword for a parallel processor-relative base address in local RAM (either data or parameter RAM). After memory allocation is performed by the linker, xba is changed to either dba (data RAM) or pba (parameter RAM), depending on where space is allocated by the linker.
XD0±XD31: External data bus pins that transfer data between the processor and external data/program memory or I/O devices of the 'C30. See also
D0±D31. (TMS320C30)
XDS: Extended development system.
XF bit: See external flag (XF) pin status bit.
XF pin: See external flag (XF) pin.
XH: See transmit buffer half transmitted (XH) bit.
XINT: See transmit interrupt (synchronous serial port).
XPT: See externally initiated packet transfer.
XRDY: See transmit ready (XRDY) bit.
XRST: See transmit reset bit.
XSR: See transmit shift register (synchronous serial port).
XSREMPTY: See transmit shift register empty (XSREMPTY) bit.
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DSP Glossary
Y
YUV: A color space standard in which the luminance (Y) and chrominance (U and V) values are separate components.
Z
zero fill: A method of filling the lowor high-order bits with zeros when loading a 16-bit number into a 32-bit field. (TMS320C62xx)
ZIF socket: Zero insertion force socket.
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