
- •Specifications
- •Introduction
- •Maximum Ratings
- •TSTG
- •Thermal characteristics
- •DC Electrical Characteristics
- •VIHC
- •VIHR
- •VIHM
- •VILC
- •VILM
- •VILS
- •ITSI
- •ICCI
- •ICCW
- •ICCS
- •3. Periodically sampled and not 100% tested
- •AC Electrical Characteristics
- •Internal Clocks
- •EThminimum
- •EThmaximum
- •ETlminimum
- •ETlmaximum
- •Icyc
- •External Clock Operation
- •Icyc
- •Phase Lock Loop (PLL) Characteristics
- •RESET, Stop, Mode Select, and Interrupt Timing
- •VIHM
- •General Purpose I/O
- •Host Interface (HI) Timing
- •6. May decrease to 0 ns for future versions
- •Serial Audio Interface (SAI) Timing
- •Master
- •Slave
- •Master
- •Slave
- •Master
- •Slave
- •Master
- •Slave
- •Master
- •Slave
- •Master
- •Slave
- •Master
- •Slave
- •Slave
- •Master
- •Slave1
- •Slave2
- •Master
- •Slave
- •Slave
- •Serial Host Interface (SHI) SPI Protocol Timing
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Slave
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Slave
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Slave
- •Master
- •Master
- •Master
- •4. Periodically sampled, not 100% tested
- •Serial Host Interface (SHI) I2C Protocol Timing
- •tSCL
- •tBUF
- •tLOW
- •tHIGH
- •Programming the Serial Clock
- •Bypassed
- •Bypassed
- •Narrow
- •Narrow
- •Wide
- •Wide
- •Bypassed
- •Narrow
- •Wide
- •tSCL
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •tBUF
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •tLOW
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •tHIGH
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Bypassed
- •Narrow
- •Wide
- •Bypassed
- •Narrow
- •Wide
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Master
- •General Purpose I/O (GPIO) Timing
- •Digital Audio Transmitter (DAX) Timing
- •Note: 1. Maximum Tl
- •2. Periodically sampled, not 100% tested

Specifications
DC Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS
Table 2-3 DC Electrical Characteristics
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Characteristics |
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Symbol |
Min |
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Typ |
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Max |
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Unit |
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Supply voltage |
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VCC |
4.75 |
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5.0 |
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5.25 |
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V |
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Input high voltage |
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VIHC |
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— |
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VCC |
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• |
EXTAL |
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4.0 |
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V |
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• |
RESET |
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VIHR |
2.5 |
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— |
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VCC |
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V |
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• |
MODA, MODB, MODC |
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VIHM |
3.5 |
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— |
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VCC |
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V |
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• |
ACI, SHI inputs1 |
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V |
IHS |
0.7 × V |
CC |
— |
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V |
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V |
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CC |
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• |
All other inputs |
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VIH |
2.0 |
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— |
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VCC |
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V |
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Input low voltage |
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VILC |
–0.5 |
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— |
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0.6 |
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V |
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• |
EXTAL |
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• |
MODA, MODB, MODC |
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VILM |
–0.5 |
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— |
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2.0 |
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V |
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• |
ACI, SHI inputs1 |
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VILS |
–0.5 |
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— |
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0.3 × VCC |
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V |
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• |
All other inputs |
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VIL |
–0.5 |
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— |
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0.8 |
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V |
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Input leakage current |
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IIN |
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A |
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• |
EXTAL, |
RESET, |
MODA, MODB, |
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–1 |
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— |
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1 |
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MODC, |
DR |
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A |
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• |
Other Input Pins (@ 2.4 V/0.4 V) |
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–10 |
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— |
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10 |
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High impedance (off-state) input current |
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ITSI |
–10 |
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— |
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10 |
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A |
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(@ 2.4 V / 0.4 V) |
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Output high voltage (IOH = –0.4 mA) |
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VOH |
2.4 |
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— |
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— |
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V |
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Output low voltage (IOL = 3.2 mA) |
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VOL |
— |
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— |
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0.4 |
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V |
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SCK/SCL IOL = 6.7 mA |
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MISO/SDA IOL = 6.7 mA |
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HOREQ |
IOL = 6.7 mA |
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Internal Supply Current @ 81 MHz |
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• |
Normal mode |
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ICCI |
— |
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135 |
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TBD |
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mA |
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• |
Wait mode |
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ICCW |
— |
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22 |
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TBD |
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mA |
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• |
Stop mode2 |
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ICCS |
— |
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5 |
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TBD |
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A |
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PLL supply current @ 81 MHz |
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— |
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1.2 |
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2.0 |
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mA |
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Input capacitance3 |
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CIN |
— |
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10 |
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— |
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pF |
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Notes: |
1. The SHI inputs are: MOSI/HA0, |
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SS/HA2, MISO/SDA, SCK/SCL, and HREQ. |
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2. |
In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL |
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signals are disabled during Stop state. |
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3. |
Periodically sampled and not 100% tested |
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MOTOROLA |
DSP56011/D |
2-3 |