Specifications
On-Chip Emulation (OnCE ) Timing
Table 2-16 OnCE Timing (Continued)
No. |
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Characteristics |
81 MHz |
Unit |
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Min |
Max |
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250A |
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assertion width to recover from Stop2 |
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DR |
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• Stable External Clock, OMR bit 6 = 0 |
15 |
65548 Tc + Tl |
ns |
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• Stable External Clock, OMR bit 6 = 1 |
15 |
20 Tc + Tl |
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• Stable External Clock, PCTL bit 17 = 1 |
15 |
13 Tc + Tl |
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250B |
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assertion width to recover from Stop and enter |
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DR |
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Debug mode2 |
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ns |
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• Stable External Clock, OMR bit 6 = 0 |
65549 Tc + Tl |
— |
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• Stable External Clock, OMR bit 6 = 1 |
21 Tc + Tl |
— |
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• Stable External Clock, PCTL bit 17= 1 |
14 Tc + Tl |
— |
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251 |
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assertion to DSO |
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valid (enter Debug |
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DR |
(ACK) |
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mode) after recovery from Stop state2 |
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• Stable External Clock, OMR bit 6 = 0 |
65553 Tc + Tl |
— |
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• Stable External Clock, OMR bit 6 = 1 |
25 Tc + Tl |
— |
ns |
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• Stable External Clock, PCTL bit 17= 1 |
18 Tc + Tl |
— |
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Note: 1. Maximum Tl
2.Periodically sampled, not 100% tested
246 |
246 |
230
DSCK
(input)
231
232
AA0277
Figure 2-22 DSP56011 OnCE Serial Clock Timing
DR (Input)
233 |
240 |
DSO |
ACK |
(Output) |
AA0278 |
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Figure 2-23 DSP56011 OnCE Acknowledge Timing
MOTOROLA |
DSP56011/D |
2-35 |
Specifications
On-Chip Emulation (OnCE ) Timing
DSCK |
(Last) |
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(OS1) |
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(Input) |
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DSO |
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(Output) |
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(ACK) |
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236 |
237 |
238 |
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DSI |
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(OS0) |
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(Input) |
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(Note 1) |
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Note: 1. High Impedance, external pull-down resistor
AA0279
Figure 2-24 DSP56011 OnCE Data I/O to Status Timing
DSCK |
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(Last) |
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(Input) |
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234 |
235 |
245 |
(Note 1) |
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DSO |
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(OS0) |
(Output) |
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Note: |
1. |
High Impedance, external pull-down resistor |
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AA0280 |
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Figure 2-25 DSP56011 OnCE Read Timing |
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OS1 |
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239 |
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(Output) |
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241 |
(Note 1) |
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(DSCK Input) |
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DSO |
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240 |
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(DSO Output) |
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(Output) |
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(DSI Input) |
OS0 |
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(Output) |
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241 |
(Note 1) |
236 |
237 |
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Note: |
1. |
High Impedance, external pull-down resistor |
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AA0281 |
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Figure 2-26 DSP56011 OnCE Data I/O Status Timing
2-36 |
DSP56011/D |
MOTOROLA |
Specifications
On-Chip Emulation (OnCE ) Timing
EXTAL (Note 2)
242
OSO–1
(Output)
(Note 1)
243 
Note: 1. High Impedance, external pull-down resistor
2. Valid when the ratio between EXTAL frequency and clock frequency equals 1
AA0282
Figure 2-27 DSP56011 OnCE EXTAL to Status Timing
DSCK (Input)
(Next Command)
244
AA0283
Figure 2-28 DSP56011 OnCE DSCK Next Command After Read Register Timing
EXTAL |
T0, T2 |
T1, T3 |
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248 |
DR |
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(Input) |
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246 |
247 |
DSO |
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(Output) |
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AA0284
Figure 2-29 Synchronous Recovery from Wait State
248
DR
(Input)
249
DSO (Output)
AA0285
Figure 2-30 Asynchronous Recovery from Wait State
MOTOROLA |
DSP56011/D |
2-37 |
Specifications
On-Chip Emulation (OnCE ) Timing
250
DR
(Input)
251
DSO (Output)
AA0286
Figure 2-31 Asynchronous Recovery from Stop State
2-38 |
DSP56011/D |
MOTOROLA |