- •Table of Contents
- •Index
- •List of Figures
- •List of Tables
- •Overview
- •1.1 Introduction
- •1.1.1 Manual Organization
- •1.1.2 Manual Conventions
- •True
- •Asserted
- •False
- •Deasserted
- •Ground2
- •True
- •Asserted
- •Ground2
- •False
- •Deasserted
- •1.2 DSP56011 Features
- •1.3 DSP56011 Architectural Overview
- •Y Data
- •Memory
- •1.3.1 Peripheral Modules
- •1.3.2 DSP Core Processor
- •1.3.2.1 Data Arithmetic and Logic Unit (Data ALU)
- •1.3.2.2 Address Generation Unit (AGU)
- •1.3.2.3 Program Control Unit
- •1.3.2.4 Data Buses
- •1.3.2.5 Address Buses
- •1.3.2.6 Phase Lock Loop (PLL)
- •1.3.3 Memories
- •1.3.3.1 Program Memory
- •1.3.3.2 X Data Memory
- •1.3.3.3 Y Data Memory
- •Program RAM
- •Program ROM
- •1.3.3.5 Memory Configuration Bits
- •1.3.3.6 External Memory
- •1.3.3.7 Bootstrap ROM
- •1.3.3.8 Reserved Memory Spaces
- •1.3.4 Input/Output
- •1.3.4.1 Parallel Host Interface (HI)
- •1.3.4.2 Serial Host Interface (SHI)
- •1.3.4.3 Serial Audio Interface (SAI)
- •1.3.4.4 General Purpose I/O
- •1.3.4.5 Digital Audio Transmitter (DAX)
- •Signal Descriptions
- •2.1 Signal Groupings
- •Port B
- •2.2 Power
- •2.3 Ground
- •2.4 Phase Lock Loop (PLL)
- •2.5 Interrupt and Mode Control
- •Input
- •1. to select the initial chip operating mode, and
- •Input
- •1. to select the initial chip operating mode, and
- •Input
- •1. to select the initial chip operating mode, and
- •Input
- •2.6 Host Interface (HI)
- •Input
- •Input
- •Input
- •Input
- •2.7 Serial Host Interface (SHI)
- •2.8 Serial Audio Interface (SAI)
- •2.8.1 SAI Receive Section
- •2.8.2 SAI Transmit Section
- •2.9 General Purpose Input/Output (GPIO)
- •2.10 Digital Audio Interface (DAX)
- •2.11 OnCE Port
- •Output
- •Input
- •Input
- •3.1 Introduction
- •3.2 DSP56011 Data and Program Memory
- •3.2.1 X and Y Data ROM
- •3.2.2 Bootstrap ROM
- •3.3 DSP56011 Data and Program Memory Maps
- •3.3.1 Reserved Memory Spaces
- •3.3.2 Dynamic Switch of Memory Configurations
- •3.3.3 Internal I/O Memory Map
- •3.4 Operating Mode Register (OMR)
- •3.5 Operating Modes
- •3.6 Interrupt Priority Register
- •3.7 Phase Lock Loop (PLL) Configuration
- •Phase
- •Detector
- •3.8 Operation on Hardware Reset
- •Parallel Host Interface
- •4.1 Introduction
- •Parallel
- •Host
- •Interface
- •4.2 Port B Configuration
- •Function
- •Port Control
- •Register Bit
- •Data Direction
- •Register Bit
- •Pin Function
- •4.2.1 Port B Control (PBC) Register
- •4.2.2 Port B Data Direction Register (PBDDR)
- •4.2.3 Port B Data (PBD) Register
- •4.3 Programming the GPIO
- •4.4 Host Interface (HI)
- •4.4.1 HI Features
- •4.4.2 HI Block Diagram
- •DSP CPU Global
- •Data Bus
- •4.4.4.1 HI Control Register (HCR)
- •4.4.4.2 HI Status Register (HSR)
- •Host to DSP56011 Status Flags
- •4.4.4.3 HI Receive Data Register (HORX)
- •4.4.4.4 HI Transmit Data Register (HOTX)
- •4.4.4.5 Register Contents After Reset
- •HCIE
- •HTIE
- •HRIE
- •HTDE
- •HRDF
- •HORX
- •X:$FFEB
- •HORX
- •HOTX
- •X:$FFEB
- •HOTX
- •4.4.4.6 DSP Interrupts
- •1. receive data register full,
- •2. transmit data register empty, and
- •3. host command.
- •4.4.5.2 Host Command
- •4.4.5.3 Interrupt Control Register (ICR)
- •Interrupt Mode
- •No Interrupts (Polling)
- •RXDF Request (Interrupt)
- •TXDE Request (Interrupt)
- •DMA Mode
- •DSP to Host Request (RX)
- •Host to DSP Request (TX)
- •Undefined (Illegal)
- •Mask
- •Interrupt Mode (DMA Off)
- •DMA Mode (24-bit)
- •DMA Mode (16-bit)
- •DMA Mode (8-bit)
- •4.4.5.4 HI Initialization
- •Interrupt Mode (HM1 = 0, HM0 = 0) INIT Execution
- •INIT = 0; Address Counter = 00
- •None
- •DSP to Host
- •Host to DSP
- •DMA Mode (HM1 or HM0 = 1) INIT Execution
- •None
- •DSP to Host
- •Host to DSP
- •Undefined (Illegal)
- •Undefined
- •4.4.5.5 Command Vector Register (CVR)
- •4.4.5.6 Interrupt Status Register (ISR)
- •4.4.5.7 Interrupt Vector Register (IVR)
- •4.4.5.8 Receive Byte Registers (RXH, RXM, RXL)
- •4.4.5.9 Transmit Byte Registers (TXH, TXM, TXL)
- •4.4.5.10 Registers After Reset
- •INIT
- •TREQ
- •RREQ
- •HOREQ
- •TRDY
- •TXDE
- •RXDF
- •4.4.6 HI Signals
- •4.4.6.3 HI Read/Write (HR/W)
- •4.4.6.4 HI Enable (HEN)
- •4.4.6.5 Host Request (HOREQ)
- •4.4.6.6 Host Acknowledge (HACK)
- •4.4.7 Servicing the HI
- •3. strobes the data transfer using HEN.
- •4.4.7.3 Polling
- •HOREQ Asserted
- •DMA ACK Gated Off
- •4.4.7.5 Servicing DMA Interrupts
- •4.4.8 Host Interface Application Examples
- •4.4.8.1 HI Initialization
- •Step 1
- •TREQ
- •RREQ
- •INIT Execution
- •2. Assert HACK (if the interface is using HACK).
- •5. Assert HEN to enable the HI.
- •5. Writing data to TXL clears TXDE in the ISR.
- •TRANSFER
- •2. The HC bit is then set.
- •4.4.8.3 DMA Data Transfer
- •1. Host asserts the HOREQ pin when TXDE = 1.
- •4.4.8.4.2 Overwriting Transmit Byte Registers
- •4.4.8.4.4 Overwriting the Host Vector
- •4.4.8.4.6 Coordinating Data Transfers
- •4.4.8.4.7 Unused Pins
- •Serial Host Interface
- •5.1 Introduction
- •5.2 Serial Host Interface Internal Architecture
- •5.3 SHI Clock Generator
- •5.4 Serial Host Interface Programming Model
- •Highest
- •Lowest
- •5.4.6.1.1 SHI Individual Reset
- •8-bit data
- •16-bit data
- •24-bit data
- •Reserved
- •5.5 Characteristics Of The SPI Bus
- •5.6 Characteristics Of The I2C Bus
- •5.6.1 Overview
- •5.7 SHI Programming Considerations
- •5.7.1 SPI Slave Mode
- •5.7.2 SPI Master Mode
- •5.7.5 SHI Operation During Stop
- •Serial Audio Interface
- •6.1 Introduction
- •6.2 Serial Audio Interface Internal Architecture
- •6.2.2 Receive Section Overview
- •6.2.3 SAI Transmit Section Overview
- •6.3 Serial Audio Interface Programming Model
- •Left Channel Transmit
- •Right Channel Transmit
- •Transmit Exception
- •Left Channel Receive
- •Right Channel Receive
- •Receive Exception
- •Highest
- •Lowest
- •6.3.1 Baud Rate Control Register (BRC)
- •6.3.2 Receiver Control/Status Register (RCS)
- •Reserved
- •6.3.3 SAI Receive Data Registers (RX0 and RX1)
- •6.3.4 Transmitter Control/Status Register (TCS)
- •Reserved
- •6.4 Programming Considerations
- •6.4.1 SAI Operation During Stop
- •6.4.2 Initiating a Transmit Session
- •6.4.4 SAI State Machine
- •GPIO
- •7.1 Introduction
- •7.2 GPIO Programming Model
- •7.3 GPIO Register (GPIOR)
- •Digital Audio Transmitter
- •8.1 Overview
- •8.2 DAX Signals
- •8.3 DAX Functional Overview
- •8.4 DAX Programming Model
- •8.5 DAX Internal Architecture
- •8.5.2 DAX Audio Data Buffer (XADBUF)
- •8.5.3 DAX Audio Data Shift Register (XADSR)
- •8.5.4 DAX Control Register (XCTR)
- •8.5.5 DAX Status Register (XSTR)
- •8.5.7 DAX Parity Generator (PRTYG)
- •8.5.8 DAX Biphase Encoder
- •8.5.9 DAX Preamble Generator
- •A (first in block)
- •8.5.10 DAX Clock Multiplexer
- •8.5.11 DAX State Machine
- •8.6 DAX Programming Considerations
- •8.6.1 Initiating A Transmit Session
- •8.6.2 Transmit Register Empty Interrupt Handling
- •8.6.3 Block Transferred Interrupt Handling
- •8.6.4 DAX Operation During Stop
- •Bootstrap ROM Contents
- •A.1 INTRODUCTION
- •A.2 BOOTSTRAPPING THE DSP
- •A.3 Bootstrap Program Listing
- •Programming Reference
- •Central Processor:
- •Parallel Host Interface
- •Serial Host Interface
- •Serial Audio Interface
- •Digital Audio Transmitter
- •A.1 Introduction
- •A.2 Peripheral Addresses
- •A.3 Interrupt Addresses
- •A.4 Interrupt Priorities
- •A.5 Instruction Set Summary
- •A.6 Programming Sheets
- •X:$FFFF
- •X:$FFFE
- •X:$FFFD
- •X:$FFFC
- •X:$FFFB
- •X:$FFFA
- •X:$FFEF
- •X:$FFEE
- •X:$FFED
- •X:$FFEC
- •X:$FFEB
- •X:$FFEA
- •X:$FFDF
- •X:$FFDE
- •X:$FFDD
- •X:$FFDC
- •X:$FFDB
- •X:$FFDA
- •Interrupt
- •Starting Address
- •Interrupt Source
- •Level 3 (Nonmaskable)
- •Levels 0, 1, 2 (Maskable)
- •Mnemonic
- •Syntax
- •Parallel Moves
- •Status Request
- •Bits:
- •Enabled
- •Multiplication Factor Bits MF0–MF11
- •Multiplication Factor MF
- •Function
- •General Purpose I/O (Reset Condition)
- •Host Interface
- •Reserved
- •Host Transmit Data Register Contents
- •Receive Data Register 0 Contents
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
Serial Audio Interface
Serial Audio Interface Programming Model
6.3SERIAL AUDIO INTERFACE PROGRAMMING MODEL
The Serial Audio Interface registers that are available to the programmer are shown in Figure 6-4. The registers are described in the following paragraphs.
Baud Rate Control Register (BRC)X: $FFE0
23 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PSR |
PM7 |
PM6 |
PM5 |
PM4 |
PM3 |
PM2 |
PM1 |
PM0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Receive Control/Status Register (RCS) X: $FFE1
23 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RRDF |
RLDF |
|
RXIL |
RXIE |
RDWT |
RREL |
RCKP |
RLRS |
RDIR |
RWL1 |
RWL0 |
RMST |
|
R1EN |
R0EN |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Transmit Control/Status Register (TCS) X: $FFE4
23 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
|
5 |
4 |
3 |
|
2 |
1 |
0 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
TRDE |
TLDE |
|
|
TXIL |
TXIE |
TDWE |
TREL |
TCKP |
TLRS |
TDIR |
TWL1 |
TWL0 |
TMST |
T2EN |
T1EN |
T0EN |
|||
|
|
|
|
|
23 |
|
|
|
|
0 |
Receiver 0 Data Register |
|
|
|
|
|||||||
|
|
Reserved Bit(s) |
|
|
|
|
|
|
|
read-only |
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
X: $FFE2 |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
23 |
|
|
|
|
0 |
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
Receiver 1 Data Register |
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
read-only |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
X: $FFE3 |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
23 |
|
|
|
|
0 |
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
Transmitter 0 Data Register |
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
write-only |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
X: $FFE5 |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
23 |
|
|
|
|
0 |
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
Transmitter 1 Data Register |
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
write-only |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
X: $FFE6 |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
23 |
|
|
|
|
0 |
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
Transmitter 2 Data Register |
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
write-only |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
X: $FFE7 |
|
|
|
|
|
|
AA0430k |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Figure 6-4 SAI Registers
The SAI interrupt vectors can be located in either of two different regions in memory. The transmit interrupt vector locations are controlled by TXIL bit in the Transmit Control Status (TCS) register. Similarly, the receive interrupt vector locations are controlled by RXIL bit in the Receive Control Status (RCS) register. The interrupt vector locations for the SAI are shown in Table 6-1. The interrupts generated by the SAI are prioritized as shown in Table 6-2.
6-8 |
DSP56011 User’s Manual |
MOTOROLA |
For More Information On This Product,
Go to: www.freescale.com