Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
Parallel Host Interface
Host Interface (HI)
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Mask |
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7 |
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0 |
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X:$FFE8 |
0 |
0 |
0 |
HF3 |
HF2 |
HCIE |
HTIE |
HRIE |
HCR |
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DSP CPU Interrupts |
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Receive Data Full |
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P:$0030 |
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Transmit Data Empty |
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P:$0032 |
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Host Command |
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P:(2 × HV → $0000–$007E) |
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Reset → HV = $0017 in CVR |
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7 |
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0 |
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X:$FFE9 |
DMA |
0 |
0 |
HF1 |
HF0 |
HCP |
HTDE |
HRDF |
HSR |
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Status |
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AA0317.11 |
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Figure 4-12 HSR and HCR Operation
4.4.5.3.5ICR HI Flag 1 (HF1)—Bit 4
The HI Flag 1 (HF1) bit is used as a general purpose flag for host-to-DSP communication. HF1 can be set or cleared by the host processor and cannot be changed by the DSP.
Note: Hardware reset, software reset, individual reset, and Stop mode clear HF1.
4.4.5.3.6ICR HI Mode Control (HM1 and HM0)—Bits 5 and 6
The HI Mode Control 1 (HM1) and HI Mode Control 0 (HM0) bits select the transfer mode of the HI (see Table 4-3). HM1 and HM0 enable the DMA mode of operation or the Interrupt (non-DMA) mode of operation.
Table 4-3 HI Mode Bit Definition
HM1 |
HM0 |
Mode |
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0 |
0 |
Interrupt Mode (DMA Off) |
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0 |
1 |
DMA Mode (24-bit) |
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1 |
0 |
DMA Mode (16-bit) |
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1 |
1 |
DMA Mode (8-bit) |
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4-26 |
DSP56011 User’s Manual |
MOTOROLA |
For More Information On This Product,
Go to: www.freescale.com