Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

LIST OF FIGURES

Figure 1-1 DSP56011 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Figure 2-1 DSP56011 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Figure 3-1 Memory Maps for PEA = 0, PEB = 0 . . . . . . . . . . . . . . . . . . . . . . 3-5 Figure 3-2 Memory Maps for PEA = 1, PEB = 0 . . . . . . . . . . . . . . . . . . . . . . 3-6

Figure 3-3 Memory Maps for PEA = 0, PEB = 1 . . . . . . . . . . . . . . . . . . . . . . 3-6 Figure 3-4 Memory Maps for PEA = 1, PEB = 1 . . . . . . . . . . . . . . . . . . . . . . 3-7 Figure 3-5 Operating Mode Register (OMR). . . . . . . . . . . . . . . . . . . . . . . . 3-11

Figure 3-6 Interrupt Priority Register (Addr X:$FFFF) . . . . . . . . . . . . . . . . 3-14 Figure 3-7 PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 Figure 4-1 Port B Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Figure 4-2 Parallel Port B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Figure 4-3 Port B GPIO Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 4-4 Figure 4-4 Port B I/O Pin Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Figure 4-5 Instructions to Write/Read Parallel Data with Port B . . . . . . . . . . 4-7

Figure 4-6 I/O Port B Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Figure 4-7 HI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Figure 4-8 HI Programming Model–DSP Viewpoint . . . . . . . . . . . . . . . . . . 4-12 Figure 4-9 HI Flag Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Figure 4-10 Host Processor Programming Model–Host Side . . . . . . . . . . . . 4-21

Freescale Semiconductor, Inc.

Figure 4-11 HI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Figure 4-12 HSR and HCR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 Figure 4-13 Command Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 Figure 4-14 Host Processor Transfer Timing. . . . . . . . . . . . . . . . . . . . . . . . . 4-35 Figure 4-15 Interrupt Vector Register Read Timing. . . . . . . . . . . . . . . . . . . . 4-38 Figure 4-16 HI Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 Figure 4-17 DMA Transfer Logic and Timing. . . . . . . . . . . . . . . . . . . . . . . . . 4-39 Figure 4-18 HI Initialization Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 Figure 4-19 HI Initialization—DSP Side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 Figure 4-20 HI Initialization—Host Side, Interrupt Mode . . . . . . . . . . . . . . . . 4-42 Figure 4-21 HI Mode and INIT Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43 Figure 4-22 HI Initialization—Host Side, Polling Mode . . . . . . . . . . . . . . . . . 4-44 Figure 4-23 HI Configuration—Host Side . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44 Figure 4-24 HI Initialization–Host Side, DMA Mode . . . . . . . . . . . . . . . . . . . 4-45 Figure 4-25 Bits Used for Host-to-DSP Transfer . . . . . . . . . . . . . . . . . . . . . . 4-46 Figure 4-26 Data Transfer from Host to DSP . . . . . . . . . . . . . . . . . . . . . . . . 4-48

Figure 4-27 Host Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50 Figure 4-28 Receive Data from Host—Main Program . . . . . . . . . . . . . . . . . . 4-51

Figure 4-29 Receive Data from Host Interrupt Routine . . . . . . . . . . . . . . . . . 4-51

Figure 4-30 Transmit/Receive Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 4-52 Figure 4-31 Bootstrap Using the Host Interface . . . . . . . . . . . . . . . . . . . . . . 4-53 Figure 4-32 Bits Used for DSP to Host Transfer . . . . . . . . . . . . . . . . . . . . . . 4-55

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Figure 6-7 Receiver Clock Polarity (RCKP) Programming . . . . . . . . . . . . . 6-13 Figure 6-8 Receiver Relative Timing (RREL) Programming . . . . . . . . . . . . 6-14 Figure 6-9 Receiver Data Word Truncation (RDWT) Programming . . . . . . 6-14 Figure 6-10 Transmitter Data Shift Direction (TDIR) Programming. . . . . . . . 6-19 Figure 6-11 Transmitter Left/Right Selection (TLRS) Programming . . . . . . . 6-19 Figure 6-12 Transmitter Clock Polarity (TCKP) Programming. . . . . . . . . . . . 6-20 Figure 6-13 Transmitter Relative Timing (TREL) Programming . . . . . . . . . . 6-20 Figure 6-14 Transmitter Data Word Expansion (TDWE) Programming. . . . . 6-21 Figure 7-1 GPIO Control/Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Figure 7-2 GPIO Circuit Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Figure 8-1 Digital Audio Transmitter (DAX) Block Diagram. . . . . . . . . . . . . . 8-4 Figure 8-2 DAX Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Figure 8-3 DAX Relative Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Figure 8-4 Preamble sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 Figure 8-5 Clock Multiplexer Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 Figure A-1 On-chip Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . B-4