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Signal/Connection Descriptions |
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Phase Lock Loop (PLL) |
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PHASE LOCK LOOP (PLL) |
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Table 1-4 Phase Lock Loop Signals |
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Signal Name |
Type |
State During |
Signal Description |
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Reset |
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PLOCK |
Output |
Indeterminate |
Phase Locked—PLOCK is an output signal that, when |
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driven high, indicates that the PLL has achieved phase |
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lock. After Reset, PLOCK is driven low until lock is |
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achieved. |
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Note: PLOCK is a reliable indicator of the PLL lock |
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state only after the chip has exited the Reset |
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state. During hardware reset, the PLOCK state is |
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determined by PINIT and the current PLL lock |
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condition. |
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PCAP |
Input |
Input |
PLL Capacitor —PCAP is an input connecting an off- |
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chip capacitor to the PLL filter. Connect one capacitor |
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terminal to PCAP and the other terminal to VCCP. |
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If the PLL is not used, PCAP may be tied to VCC, GND, |
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or left floating. |
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PINIT |
Input |
Input |
PLL Initial —During assertion of |
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the value of |
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RESET, |
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PINIT is written into the PLL Enable (PEN) bit of the PLL |
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Control Register, determining whether the PLL is |
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enabled or disabled. |
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EXTAL |
Input |
Input |
External Clock/Crystal Input —EXTAL interfaces the |
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internal crystal oscillator input to an external crystal or |
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an external clock. |
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MOTOROLA |
DSP56011/D |
1-5 |