
- •Advance Information
- •Y Data
- •Memory
- •Figure 1 DSP56011 Block Diagram
- •Table of Contents
- •Features
- •Digital Signal Processing Core
- •Memory
- •Program RAM
- •X data RAM
- •Y data RAM
- •Program ROM
- •X data ROM
- •Y data ROM
- •Peripheral and Support Circuits
- •Documentation
- •DSP56KFAMUM/AD
- •Signal/Connection Descriptions
- •Signal Groupings
- •Port B
- •Power
- •Ground
- •Phase Lock Loop (PLL)
- •Interrupt and Mode Control
- •Input
- •Input
- •Input (MODA)
- •Input
- •Input
- •Input (MODB)
- •Input (MODC)
- •Input
- •Host Interface (HI)
- •Input
- •Input
- •Input
- •Input
- •Serial Host Interface (SHI)
- •Serial Audio Interface (SAI)
- •SAI Receive Section
- •SAI Transmit Section
- •General Purpose Input/Output (GPIO)
- •Digital Audio Interface (DAX)
- •OnCE Port
- •Input
- •Output
- •Input
- •Output
- •Output
- •Input
- •Input
- •Specifications
- •Introduction
- •Maximum Ratings
- •TSTG
- •Thermal characteristics
- •DC Electrical Characteristics
- •VIHC
- •VIHR
- •VIHM
- •VILC
- •VILM
- •VILS
- •ITSI
- •ICCI
- •ICCW
- •ICCS
- •3. Periodically sampled and not 100% tested
- •AC Electrical Characteristics
- •Internal Clocks
- •ETHminimum
- •ETHmaximum
- •ETLminimum
- •ETLmaximum
- •ICYC
- •External Clock Operation
- •ICYC
- •Phase Lock Loop (PLL) Characteristics
- •RESET, Stop, Mode Select, and Interrupt Timing
- •VIHM
- •General Purpose I/O
- •Host Interface (HI) Timing
- •6. May decrease to 0 ns for future versions
- •Serial Audio Interface (SAI) Timing)
- •Master
- •Slave
- •Master
- •Slave
- •Master
- •Slave
- •Master
- •Slave
- •Master
- •Slave
- •Master
- •Slave
- •Master
- •Slave
- •Slave
- •Master
- •Slave1
- •Slave2
- •Master
- •Slave
- •Slave
- •Serial Host Interface (SHI) SPI Protocol Timing
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Slave
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Slave
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Slave
- •Master
- •Master
- •Master
- •4. Periodically sampled, not 100% tested
- •Serial Host Interface (SHI) I2C Protocol Timing
- •TSCL
- •TBUF
- •TLOW
- •THIGH
- •Programming the Serial Clock
- •Bypassed
- •Narrow
- •Wide
- •Bypassed
- •Narrow
- •Wide
- •Bypassed
- •Narrow
- •Wide
- •Bypassed
- •Narrow
- •Wide
- •Bypassed
- •Narrow
- •Wide
- •TSCL
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •TBUF
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •TLOW
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •THIGH
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Bypassed
- •Narrow
- •Wide
- •Bypassed
- •Narrow
- •Wide
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Slave
- •Bypassed
- •Narrow
- •Wide
- •Master
- •Bypassed
- •Narrow
- •Wide
- •Master
- •General Purpose Input/Output (GPIO) Timing
- •Digital Audio Transmitter (DAX) Timing
- •2. Periodically sampled, not 100% tested
- •Note: High Impedance, external pull-down resistor
- •Packaging
- •Pin-out and Package Information
- •TQFP Package Description
- •not connected
- •MOSI/HA0
- •GPIO7
- •not connected
- •GPIO6
- •GNDA
- •GNDH
- •HREQ
- •GNDD
- •not connected
- •VCCH
- •GNDS
- •GPIO5
- •not connected
- •GPIO4
- •VCCD
- •not connected
- •GPIO3
- •GNDH
- •not connected
- •VCCS
- •GPIO2
- •not connected
- •SCKT
- •GNDD
- •VCCH
- •PLOCK
- •GPIO1
- •VCCQ
- •SCKR
- •GPIO0
- •GNDQ
- •GNDQ
- •GNDQ
- •PINIT
- •VCCQ
- •VCCQ
- •VCCQ
- •GNDP
- •GNDS
- •not connected
- •GNDQ
- •PCAP
- •not connected
- •HACK/PB14
- •VCCP
- •GNDA
- •GNDH
- •EXTAL
- •not connected
- •VCCA
- •GNDS
- •not connected
- •VCCH
- •MISO/SDA
- •DSCK/OS1
- •not connected
- •RESET
- •not connected
- •GNDA
- •not connected
- •not connected
- •GNDH
- •MODB/IRQB
- •not connected
- •not connected
- •MODC/NMI
- •not connected
- •not connected
- •VCCS
- •GPIO7
- •not connected
- •not connected
- •PCAP
- •not connected
- •PINIT
- •DSCK
- •not connected
- •PLOCK
- •not connected
- •RESET
- •not connected
- •EXTAL
- •not connected
- •SCKR
- •GNDA
- •not connected
- •SCKT
- •GNDA
- •not connected
- •GNDA
- •not connected
- •GNDD
- •not connected
- •GNDD
- •HACK
- •not connected
- •GNDH
- •not connected
- •GNDH
- •not connected
- •GNDH
- •not connected
- •GNDH
- •GNDP
- •HOREQ
- •VCCA
- •GNDQ
- •HREQ
- •GNDQ
- •VCCD
- •GNDQ
- •IRQA
- •VCCH
- •GNDQ
- •IRQB
- •VCCH
- •GNDS
- •MISO
- •VCCH
- •GNDS
- •MODA
- •VCCP
- •GNDS
- •MODB
- •VCCQ
- •GPIO0
- •MODC
- •VCCQ
- •GPIO1
- •MOSI
- •VCCQ
- •GPIO2
- •VCCQ
- •GPIO3
- •not connected
- •VCCS
- •GPIO4
- •not connected
- •VCCS
- •GPIO5
- •not connected
- •GPIO6
- •not connected
- •Ordering Drawings
- •Design Considerations
- •Thermal Design Considerations
- •Electrical Design Considerations
- •Power Consumption Considerations
- •Power-Up Considerations
- •Host Port Considerations
- •Host Programming Considerations
- •DSP Programming Considerations
- •Ordering Information

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Signal/Connection Descriptions |
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General Purpose Input/Output (GPIO) |
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GENERAL PURPOSE INPUT/OUTPUT (GPIO) |
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Table 1-10 General Purpose I/O (GPIO) Signals |
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Signal |
Signal Type |
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State during |
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Signal Description |
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Name |
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Reset |
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GPIO0– |
Input or |
Disconnected |
General Purpose Input/Output—These signals |
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GPIO7 |
Output |
internally |
are used for control and handshake functions |
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(standard or |
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between the DSP and external circuitry. Each |
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open-drain) |
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GPIO signal may be individually programmed to |
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be one of four states: |
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• |
Not connected |
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• |
Input |
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• |
Standard output |
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• Open-drain output |
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DIGITAL AUDIO INTERFACE (DAX) |
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Table 1-11 Digital Audio Interface (DAX) Signals |
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Signal Name |
Type |
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State During |
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Signal Description |
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Reset |
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ADO |
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Output |
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Output, driven |
Digital Audio Data Output—This signal is an |
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high |
audio and non-audio output in the form of AES/ |
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EBU, CP340 and IEC958 data in a biphase mark |
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format. The signal is driven high when the DAX is |
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disabled, and during hardware or software reset. |
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ACI |
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Input |
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Tri-stated |
Audio Clock Input—This is the DAX clock input. |
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When programmed to use an external clock, this |
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input supplies the DAX clock. The external clock |
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frequency must 256, 384, or 512 times the audio |
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sampling frequency (256 x Fs, 384 x Fs or 512 x Fs, |
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respectively). The ACI signal is high impedance |
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(tri-stated) only during hardware or software reset. |
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If the DAX is not used, connect the ACI signal to |
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ground through an external pull-down resistor to |
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ensure a stable logic level at the input. |
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Preliminary Information
MOTOROLA |
DSP56011 Technical Data Sheet, Rev. 1 |
1-17 |