Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
Timer Inputs
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PINHL |
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PINHL |
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Timer Outputs
POUT |
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POUTHL |
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POUTHL |
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Figure 29. Quad Timer Timing
3.13 Serial Communication Interface (SCI) Timing
Table 20. SCI Timing4
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85° C, CL ≤ |
50pF, fop = 80MHz |
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Characteristic |
Symbol |
Min |
Max |
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Unit |
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Baud Rate1 |
BR |
— |
(fMAX*2.5)/(80) |
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Mbps |
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RXD2 Pulse Width |
RXDPW |
0.965/BR |
1.04/BR |
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ns |
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TXD3 Pulse Width |
TXDPW |
0.965/BR |
1.04/BR |
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1.fMAX is the frequency of operation of the system clock in MHz.
2.The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3.The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4.Parameters listed are guaranteed by design.
RXD |
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SCI receive |
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data pin |
RXDPW |
(Input) |
Figure 30. RXD Pulse Width
TXD |
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SCI receive |
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data pin |
TXDPW |
(Input) |
Figure 31. TXD Pulse Width
42 56F827 Technical Data
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
JTAG Timing
3.14 JTAG Timing
Table 21. JTAG Timing1, 3
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85° C, CL ≤ |
50pF, fop = 80MHz |
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Characteristic |
Symbol |
Min |
Max |
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Unit |
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TCK frequency of operation2 |
fOP |
DC |
10 |
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MHz |
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TCK cycle time |
tCY |
100 |
— |
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TCK clock pulse width |
tPW |
50 |
— |
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ns |
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TMS, TDI data set-up time |
tDS |
0.4 |
— |
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ns |
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TMS, TDI data hold time |
tDH |
1.2 |
— |
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ns |
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TCK low to TDO data valid |
tDV |
— |
26.6 |
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ns |
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TCK low to TDO tri-state |
tTS |
— |
23.5 |
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ns |
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assertion time |
tTRST |
50 |
— |
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ns |
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TRST |
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assertion time |
tDE |
4T |
— |
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ns |
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DE |
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1.Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2.TCK frequency of operation must be less than 1/8 the processor rate.
3.Parameters listed are guaranteed by design.
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tCY |
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tPW |
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tPW |
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VIH |
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TCK |
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VM |
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VM |
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(Input) |
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VIL |
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VM = VIL + (VIH – VIL)/2 |
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Figure 32. Test Clock Input Timing Diagram
56F827 Technical Data |
43 |
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
TCK (Input)
TDI
TMS 
(Input)
TDO (Output)
TDO (Output)
TDO (Output)
TRST
(Input)
DE
Freescale Semiconductor, Inc.
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tDS |
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tDH |
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Input Data Valid
tDV
Output Data Valid
tTS
tDV
Output Data Valid
Figure 33. Test Access Port Timing Diagram
tTRST
Figure 34. TRST Timing Diagram
tDE
Figure 35. OnCE—Debug Event
44 56F827 Technical Data
For More Information On This Product,
Go to: www.freescale.com