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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

DSP56F827/D

Rev. 9.0, 02/2004

56F827

Technical Data

56F827 16-bit Hybrid Controller

Up to 40 MIPS at 80MHz core frequency

DSP and MCU functionality in a unified, C-efficient architecture

Hardware DO and REP loops

64K × 16-bit words Program Flash

1K × 16-bit words Program RAM

4K × 16-bit words Data Flash

4K × 16-bit words Data RAM

Up to 64K × 16-bit words external memory expansion each for Program and Data memory

JTAG/OnCE™ for debugging

General Purpose Quad Timer

MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes

8-channel Programmable Chip Select

10-channel, 12-bit ADC

Synchronous Serial Interface (SSI)

Serial Port Interface (SPI)

Serial Communications Interface (SCI)

Time-of-Day (TOD) Timer

128-pin LQFP Package

16-dedicated and 48 shared GPIO

 

 

 

 

EXTBOOT

DEBUG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

IRQB

 

 

VDDIO

VSSIO

VDD

VSS

VDDA

VSSA

 

 

 

 

 

IRQA

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

5

3

4

2

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

inputs

 

 

 

 

 

JTAG/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low Voltage Supervisor

Analog Reg

 

 

 

10

 

 

 

 

 

OnCE

 

 

 

 

 

 

 

 

 

VREFP, VREFMID,

ADC

 

 

 

 

Port

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREFIN

3

 

Interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data ALU

 

 

Bit

 

 

 

VREFLO

 

Controller

Program Controller

Address

 

 

 

 

 

 

 

 

 

and Hardware

Generation

16 x 16 + 36 →

36-Bit MAC

Manipulation

 

 

 

 

 

 

Three 16-bit Input Registers

Unit

 

 

 

 

 

 

Looping Unit

Unit

 

 

 

 

VREFHI

 

 

 

Two 36-bit Accumulators

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Program and Boot

 

 

PAB

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory

 

 

PDB

 

 

 

 

16-Bit

 

 

 

CLKO

 

 

Quad Timer A/

64512 x 16 Flash

 

 

 

 

 

 

 

PLL

 

 

4

 

 

 

 

 

 

 

56800

 

 

 

or GPIO

1024 x 16 SRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Core

 

 

 

 

 

VPP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XDB2

 

 

 

 

 

 

 

Clock

 

XTAL

 

 

 

Data Memory

 

 

CGDB

 

 

 

 

 

 

 

 

 

 

SCI 2 or

 

 

XAB1

 

 

 

 

 

 

 

Gen

 

 

 

 

4096 x 16 Flash

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXTAL

 

2

GPIO

4096 x 16 SRAM

 

 

XAB2

 

 

 

 

 

 

 

 

 

 

 

 

INTERRUPT

 

IPBB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSI 0 or

 

 

 

CONTROLS

CONTROLS

 

 

 

 

 

 

 

6

GPI0

 

 

 

 

16

 

 

16

 

 

External

 

A[00:15]

 

 

 

 

 

COP

 

 

 

 

 

 

 

 

 

 

SCI 0 &1 or

 

 

 

 

 

 

 

External

Address Bus

 

or

 

 

COP/

 

RESET

 

 

 

 

 

Switch

16

GPIOA16[00:16]

 

4

SPI 0

 

 

 

 

 

 

Bus

 

Watchdog

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MODULE

 

 

 

 

Interface

 

 

 

 

 

 

SPI 1 or

Application-

IPBus Bridge

 

 

 

 

 

 

CONTROLS

Unit

External

 

D[00:15]

 

4

GPIO

Specific

 

 

 

(IPBB)

 

 

 

Data Bus

 

or

 

 

 

 

 

 

 

 

 

PCS [2:7}

Programmable

Memory &

ADDRESS

 

 

 

 

 

 

Switch

16

GPIOG16[00:16]

 

 

 

 

 

 

 

 

 

 

 

6

Chip Select

Peripherals

BUS [8:0]

 

 

 

 

 

 

 

 

 

PS or PCS[0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dedicated

 

 

DATA

 

 

 

 

 

 

 

Bus

 

DS or PCS[1]

 

 

TOD

 

 

 

 

 

 

 

 

Control

 

WR

 

16

GPIO

BUS [15:0]

 

 

 

 

 

 

 

 

Timer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1. 56F827 Block Diagram

© Motorola, Inc., 2004. All rights reserved.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Part 1 Overview

1.1 56F827 Features

1.1.1Digital Signal Processing Core

Efficient 16-bit 56800 family DSP engine with dual Harvard architecture

As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

Two 36-bit accumulators including extension bits

16-bit bidirectional shifter

Parallel instruction set with unique DSP addressing modes

Hardware DO and REP loops

Three internal address buses and one external address bus

Four internal data buses and one external data bus

Instruction set supports both DSP and controller functions

Controller style addressing modes and instructions for compact code

Efficient C Compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/OnCE Debug Programming Interface

1.1.2Memory

Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

On-chip memory including a low-cost, high-volume Flash solution

64K words of Program Flash

1K words of Program RAM

4K words of Data RAM

4K words of Data Flash

Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

As much as 64 K × 16 Data memory

As much as 64 K × 16 Program memory

1.1.3Peripheral Circuits for 56F827

One 10 channel, 12-bit, Analog-to-Digital Converter (ADC)

One General Purpose Quad Timer totaling 4 pins

One Serial Peripheral Interface with configurable four-pin port multiplexed with two Serial Communications Interfaces totalling 4 pins or 4 GPIO pins

Three Serial Communication Interfaces with 2 pins each (or 6 additional GPIO pins)

Two Serial Peripheral Interface with configurable four-pin port (or 4 additional GPIO pins)

2 56F827 Technical Data

For More Information On This Product,

Go to: www.freescale.com

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