
- •Part 1 Overview
- •1.1 56F827 Features
- •1.1.1 Digital Signal Processing Core
- •1.1.2 Memory
- •1.1.3 Peripheral Circuits for 56F827
- •1.1.4 Power Information
- •1.2 56F827 Description
- •1.3 Award-Winning Development Environment
- •1.4 Product Documentation
- •1.5 Data Sheet Conventions
- •Part 2 Signal/Connection Descriptions
- •2.1 Introduction
- •2.2 Signals and Package Information
- •Part 3 Specifications
- •3.1 General Characteristics
- •3.2 DC Electrical Characteristics
- •3.3 Supply Voltage Sequencing and Separation Cautions
- •3.4 AC Electrical Characteristics
- •3.5 Flash Memory Characteristics
- •3.6 External Clock Operation
- •3.6.1 Crystal Oscillator
- •3.6.2 Ceramic Resonator
- •3.6.3 External Clock Source
- •3.6.4 Phase Locked Loop Timing
- •3.7 External Bus Asynchronous Timing
- •3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
- •3.9 Serial Peripheral Interface (SPI) Timing
- •3.10 Analog-to-Digital Converter (ADC) Timing
- •3.11 SSI Timing
- •3.12 Quad Timer Timing
- •3.13 Serial Communication Interface (SCI) Timing
- •3.14 JTAG Timing
- •Part 4 Packaging
- •4.1 Package and Pin-Out Information 56F827
- •Part 5 Design Considerations
- •5.1 Thermal Design Considerations
- •5.2 Electrical Design Considerations
- •Part 6 Ordering Information

Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
DSP56F827/D
Rev. 9.0, 02/2004
56F827
Technical Data
56F827 16-bit Hybrid Controller
•Up to 40 MIPS at 80MHz core frequency
•DSP and MCU functionality in a unified, C-efficient architecture
•Hardware DO and REP loops
•64K × 16-bit words Program Flash
•1K × 16-bit words Program RAM
•4K × 16-bit words Data Flash
•4K × 16-bit words Data RAM
•Up to 64K × 16-bit words external memory expansion each for Program and Data memory
•JTAG/OnCE™ for debugging
•General Purpose Quad Timer
•MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes
•8-channel Programmable Chip Select
•10-channel, 12-bit ADC
•Synchronous Serial Interface (SSI)
•Serial Port Interface (SPI)
•Serial Communications Interface (SCI)
•Time-of-Day (TOD) Timer
•128-pin LQFP Package
•16-dedicated and 48 shared GPIO
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EXTBOOT |
DEBUG |
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RESET |
IRQB |
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VDDIO |
VSSIO |
VDD |
VSS |
VDDA |
VSSA |
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IRQA |
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6 |
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JTAG/ |
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Low Voltage Supervisor |
Analog Reg |
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10 |
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OnCE |
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VREFP, VREFMID, |
ADC |
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Port |
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VREFIN |
3 |
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Interrupt |
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Data ALU |
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Bit |
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VREFLO |
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Controller |
Program Controller |
Address |
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and Hardware |
Generation |
16 x 16 + 36 → |
36-Bit MAC |
Manipulation |
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Three 16-bit Input Registers |
Unit |
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Looping Unit |
Unit |
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VREFHI |
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Two 36-bit Accumulators |
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Program and Boot |
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PAB |
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Memory |
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PDB |
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16-Bit |
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CLKO |
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Quad Timer A/ |
64512 x 16 Flash |
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PLL |
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4 |
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56800 |
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or GPIO |
1024 x 16 SRAM |
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Core |
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VPP |
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XDB2 |
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Clock |
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XTAL |
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Data Memory |
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CGDB |
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SCI 2 or |
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XAB1 |
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Gen |
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4096 x 16 Flash |
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EXTAL |
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GPIO |
4096 x 16 SRAM |
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XAB2 |
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INTERRUPT |
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IPBB |
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SSI 0 or |
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CONTROLS |
CONTROLS |
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6 |
GPI0 |
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16 |
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16 |
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External |
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A[00:15] |
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COP |
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SCI 0 &1 or |
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External |
Address Bus |
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COP/ |
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RESET |
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Switch |
16 |
GPIOA16[00:16] |
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4 |
SPI 0 |
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Bus |
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Watchdog |
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MODULE |
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Interface |
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SPI 1 or |
Application- |
IPBus Bridge |
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CONTROLS |
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External |
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D[00:15] |
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4 |
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(IPBB) |
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Data Bus |
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PCS [2:7} |
Programmable |
Memory & |
ADDRESS |
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Switch |
16 |
GPIOG16[00:16] |
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6 |
Chip Select |
Peripherals |
BUS [8:0] |
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PS or PCS[0] |
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Dedicated |
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DATA |
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Bus |
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DS or PCS[1] |
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TOD |
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Control |
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WR |
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16 |
GPIO |
BUS [15:0] |
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Timer |
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RD |
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Figure 1. 56F827 Block Diagram
© Motorola, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com

Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
Part 1 Overview
1.1 56F827 Features
1.1.1Digital Signal Processing Core
•Efficient 16-bit 56800 family DSP engine with dual Harvard architecture
•As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
•Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
•Two 36-bit accumulators including extension bits
•16-bit bidirectional shifter
•Parallel instruction set with unique DSP addressing modes
•Hardware DO and REP loops
•Three internal address buses and one external address bus
•Four internal data buses and one external data bus
•Instruction set supports both DSP and controller functions
•Controller style addressing modes and instructions for compact code
•Efficient C Compiler and local variable support
•Software subroutine and interrupt stack with depth limited only by memory
•JTAG/OnCE Debug Programming Interface
1.1.2Memory
•Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
•On-chip memory including a low-cost, high-volume Flash solution
—64K words of Program Flash
—1K words of Program RAM
—4K words of Data RAM
—4K words of Data Flash
•Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
—As much as 64 K × 16 Data memory
—As much as 64 K × 16 Program memory
1.1.3Peripheral Circuits for 56F827
•One 10 channel, 12-bit, Analog-to-Digital Converter (ADC)
•One General Purpose Quad Timer totaling 4 pins
•One Serial Peripheral Interface with configurable four-pin port multiplexed with two Serial Communications Interfaces totalling 4 pins or 4 GPIO pins
•Three Serial Communication Interfaces with 2 pins each (or 6 additional GPIO pins)
•Two Serial Peripheral Interface with configurable four-pin port (or 4 additional GPIO pins)
2 56F827 Technical Data
For More Information On This Product,
Go to: www.freescale.com