Module Memory Map

Table 4-5. Test Inputs/Outputs

Table 4-6. Derived Clock Inputs

4.5 Module Memory Map

The System Integration Module (SIM) contains four programmable 16-bit registers. The address range from X:$1FFF08 to X:$1FFF0F is allocated to the SIM. The register accessed by each of the eight-memory mapped addresses is indicated in Table 4-7. A write to an address without an associated register is a NOOP. A read from an address without an associated register returns unknown data.

Table 4-7. SIM Module Memory Map (SIM_BASE =$FFF08)

Register Descriptions (SYS_BASE = $1FFF08)

Figure 4-2. SCI Register Map Summary

4.6 Register Descriptions (SYS_BASE = $1FFF08)

4.6.1 SIM Control Register (SCR)

Figure 4-8. SIM Control Register (SCR)

See Programmer’s Sheet on Appendix page B-6

4.6.1.1 Reserved—Bit 15

This bit is reserved or not implemented. It is read as 0, but cannot be modified by writing.

4.6.1.2 Boot Mode—Bits 14–12

Note: This field replaces the mode bits in the 56852 OMR.

This field is set to the value of external pads D[15:13] when the last active reset source reset pin, power-on reset, or software reset deasserts.

Note: A COP reset via RST_COP does not alter these registers since a COP reset by definition occurs unexpectedly during system operation. Users may no longer be providing the required MODE_CBA inputs.

Note: A software reset via RST_SW does not alter these registers, thereby allowing a reboot in a different mode without altering the hardware.

Register Descriptions (SYS_BASE = $1FFF08)

The 56800E core always begins execution from the base of the on-chip ROM. The software in ROM will perform one of several boot actions based on the value of BOOT MODE.

The bootstrap program expects the following prefix data-sequence when downloading the user program through an external port.

1.The 4-byte string $43, $4F, $4F, $54 (Boot mode 1 only)

2.Two words (4 bytes) defining the number of program words to be loaded (Boot modes 0, 1, and 6)

3.Two words (4 bytes) starting address the program memory will be loaded in by the user program (Boot modes 0, 1, and 6)

The user program follows two bytes for each 16-bit program word.

The bytes/words for each data sequence are loaded least significant byte/word first. The boot code is general-purpose and assumes the number of program words and starting address are valid for the users system. If the values are invalid then unpredictable results will occur. If a Reserved mode is specified, the 56800E DEBUGHLT instruction will be executed to place the core in Debug mode.

Once the bootstrap program completes loading the specified number of words, it jumps to the starting address to execute the loaded program. Some of the bootstrap routines also reconfigure the memory map by setting the PRAM Disable and/or DRAM Disable fields.

4.6.1.2.1 Boot Mode 0: Bootstrap from Byte Wide External Memory

The PRAM DISABLE and DRAM DISABLE fields are both left zero, leaving both internal program and Data RAM enabled. The Bootstrap program loads program memory from a byte-wide memory located at X:$040000 then jumps to the start of the user code.

4.6.1.2.2 Boot Mode 1: Bootstrap from SPI Port

The PRAM DISABLE and DRAM DISABLE remains zero, leaving both internal program and Data RAM enabled. The bootstrap program loads program memory from a serial EEPROM via the SPI. GPIOC3 is an alternative function of the SS, which when configured and programmed, can be used as the SS output. This mode is compatible with ATMEL AT25xxx, AT25xxxx, and AT45xxx series serial EEPROMs. After loading the user program, GPIOC3 is returned to its power on reset state (input under peripheral control) and the Bootstrap program jumps to the start of the user code. Boot Mode 1 requires extra header data described in Section 4.6.1.2.

Register Descriptions (SYS_BASE = $1FFF08)

4.6.1.2.3 Boot Mode 2: Normal Expanded Mode

The PRAM DISABLE and DRAM DISABLE fields are both left zero, leaving both internal program and Data RAM enabled. No code is loaded. The Bootstrap program simply vectors to external program memory location P:$040000.

4.6.1.2.4 Boot Mode 3: Development Expanded Mode

The DRAM DISABLE field is left zero, but PRAM DISABLE is set to 1. This leaves the Internal Data RAM enabled but the Internal Program RAM disabled. All references to internal program memory space are subsequently directed to the external program memory. No code is loaded. The Bootstrap program simply vectors to program memory location P:$000000.

4.6.1.2.5 Boot Modes 4–5: Reserved

These bits are reserved for future use.

4.6.1.2.6 Boot Mode 6: Bootstrap from SCI Port

Mode 6 is one of the Bootstrap mode having all internal program and data RAM memories enabled. In Mode 6, the bootstrap program loads program memory from an asynchronous serial peripheral device via the SCI. This mode requires a specific crystal to be used with the PLL for clock generation. If a 4MHz crystal is used, the data rate of the SCI is 38400. Consequently, a 2MHz crystal yields a data rate of 19200. In future versions, a baud detection program with handshaking should be added. The data format is:

•One start bit

•Eight-data bits

•No parity bit

•One Stop bit

•Flow Control off

After loading the user program, the bootstrap program jumps to the start of the user code.

4.6.1.2.7 Reserved: Boot Mode 7

This bit is reserved for future use.

4.6.1.3 Reserved—Bits 11–7

Bits 11–8 are read only 0 and cannot be modified. Bit 7, however, can be modified and initializes to 1. It currently serves no functional purpose.

Register Descriptions (SYS_BASE = $1FFF08)

4.6.1.4 Enhanced OnCE Enable (OnCE_EBL)—Bit 6

Set if the Enhanced OnCE register I/O or other Enhanced OnCE features to be used from application software rather than the external debugger attached to the TAP interface.

•0 = Enhanced OnCE clock to core enabled when the core TAP is enabled

•1 = Enhanced OnCE clock to core is always enabled

4.6.1.5 CLKOUT Disable (CLKOUT_DBL)—Bit 5

• 0 = CLKOUT output pin presents CLK_MSTR/8 (this is half the peripheral bus clock frequency)

• 1 = CLKOUT output presents static zero

4.6.1.6 Program RAM Disable (PRAM_DBL)—Bit 4

• 0 = Internal program RAM enabled

• 1 = Internal program RAM disabled and accesses redirected to external memory

4.6.1.7 Data RAM Disable (DRAM_DBL)—Bit 3

•0 = Internal data RAM enabled

•1 = Internal data RAM disabled and accesses redirected to external memory

4.6.1.8 Software Reset (SW_RST)—Bit 2

Writing 1 to this field resets the part.

4.6.1.9 Stop Disable (STOP_DBL)—Bit 1

The Stop mode will be entered when the core executes a Stop instruction.

•0 = The Stop instruction will cause entry into Stop mode

•1 = The Stop instruction will not cause entry into Stop mode

4.6.1.10 Wait Disable (WAIT_DBL)—Bit 0

The Wait mode will be entered when the core executes a Wait instruction.

•0 = The Wait instruction will cause entry into the Wait mode

•1 = The Wait instruction will not cause entry into the Wait mode

Register Descriptions (SYS_BASE = $1FFF08)

4.6.2 SIM Software Control Data 1 (SCD1)

Figure 4-9. SIM Software Control Data Register 1 (SCD1)

See Programmer’s Sheet on Appendix page B-7

4.6.2.1 Software Control Data 1 (SSCR1)—Bits 15–0

This register is reset only by the Power-On Reset (POR). It has no part specific functionality and is intended for use by software developers to contain data to be unaffected by the other reset sources:

•Reset pin

•Software reset

•COP reset

4.6.3 Software Control Data 2 (SCD2)

Figure 4-10. SIM Software Control Data Register 2 (SCD2)

See Programmer’s Sheet on Appendix page B-7

4.6.3.1 Software Control Data 2 (SCD2)—Bits 15–0

This register is reset only by the Power-on Reset (POR). It has no part specific functionality and is intended for use by software developers to contain data to be unaffected by the other reset sources:

•Reset pin

•Software reset

•COP reset

Register Descriptions (SYS_BASE = $1FFF08)

4.6.4 SIM Configuration Register (SCFGR)

1.Since date code 0302, the ROM Bootcode of the device will change the setting of CFG A[19} to one. It will then be configured as CS3 and be set to the inactive state, 1. Exercise care when using Boot Mode 2 taking this into consideration.

Figure 4-11. SIM Configuration Register (SCFGR)

See Programmer’s Sheet on Appendix page B-8

The Configuration register determines which of two functional signals is connected to a specific bidirectional external I/O device during the normal (functional) operating mode of the part. These external I/O and the Configuration register bit fields are named for the signal connected to that I/O by default.

4.6.4.1 Reserved—Bits 15–8

These bits are reserved or not implemented. They cannot be read nor modified by writing.

4.6.4.2 Configure Clock Out (CFG_CLKOUT)—Bit 7

•0 = CLKOUT (SIM)

•1 = A[20] (EMI)

4.6.4.3 Configure A[19] Output (CFG_A[19])—Bit 6

•0 = A[19] (EMI)

•1 = CS3 (EMI)

4.6.4.4 Configure A[18] Output (CFG_A[18])—Bit 5

•0 = A[18] (EMI)

•1 = TIO1 (TMR)

4.6.4.5 Configure A[17] Output (CFG_A[17])—Bit 4

•0 = A[17] (EMI)

•1 = TIO0 (TMR)

4.6.4.6 Configure Serial Clock (CFG_SCLK)—Bit 3

•0 = SCK (SPI)

•1 = STCK (SSI)