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Features

4.1 Introduction

The System Integration Module (SIM) is responsible for system control functions listed below:

Clock generation

Reset generation

Power mode control

Boot mode control

Memory map control

Integrated Circuit (IC) configuration control

External I/O configuration control

Software control registers

4.2Features

The SIM module provides these listed qualities:

Four system bus clocks with pipeline hold-off support

Data RAM clock with hold-off control

IPBus Interface clock with hold-off control

Core system clock

General purpose clock (both standard and inverted versions)

Three system clocks for non-pipelined interfaces

PCLK clock for core

NCLK clock for core

A continuously running system clock

A peripheral bus (IPBus) clock, both standard and inverted versions

An external clock output with disable

A peripheral bus clock phase indicator

Three power modes to control power utilization:

Stop mode shuts down core, system clocks, and peripheral bug clocks. Stop mode entry can optionally disable PLL and Oscillator (lowest power vs. fast restart).

Wait mode shuts down the core, and unnecessary system clock operation while peripherals continue to operate.

 

System Integration Module (SIM), Rev. 4

Freescale Semiconductor

4-3

-packaged product lines and part numbers indicated here currently are not

2010: MC13892

Commission, BGA

prior to September

order from the United States International Trade Freescale for import or sale in the United States

of an from

Because

available

Features

Run mode supports full part operation

Controls to enable/disable the core Wait and Stop instructions

32-cycle extended synchronous resets for CGM, the core, and other system blocks

Software initiated reset

Controls to redirect internal data and/or program RAM accesses to the external memory interface

Software Boot mode control register (initialized at any reset except COP reset from external pads)

A hold-off output to coordinate the system and peripheral buses

Two 16-bit software control registers reset only by a power-on reset usable for general purpose software control

Eight bits to control external I/O configurations

Features to support testing of the SIM and the IC

Scan test support

JTAG boundary scan

Peripheral Broadside Test mode

 

56852 Digital Signal Controller User Manual, Rev. 4

4-4

Freescale Semiconductor

-packaged product lines and part numbers indicated here currently are not

2010: MC13892

Commission, BGA

prior to September

order from the United States International Trade Freescale for import or sale in the United States

of an from

Because

available

SIM Block Diagram

4.3 SIM Block Diagram

The System Integration Module (SIM) is depicted in Table 4-1.

 

 

 

 

CFG_*

 

Configuration Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Software Control Reg 1

 

 

 

 

 

 

 

IPBus

Bus

Software Control Reg 2

 

Interface

 

 

 

 

 

 

 

Modes A, B, C

 

 

SIM Control Register

P/D RAM Disable

 

 

 

Stop/Wait Disable

 

 

 

IPBus Slow Write

 

Master CLK

 

Pipelined Sys Clks

 

Scan CLK

 

 

 

Other Sys Clks

 

IPBB Hold-Off

 

 

Clock Generator

56800E Clks

 

XRAM Hold-Off

 

Core Stall

 

Periph Bus Clk

 

 

Periph Bus Phase

 

CLKOUT Disable

 

 

 

Hold-Off

 

NCLK Enable

 

 

 

Cont Sys Clk*

 

 

 

 

 

 

Internal Clk

 

POR Disable

 

Reset POR

 

 

Reset Internal

 

Reset SW

Reset Generator

 

Reset Core

 

Reset Pin

 

Reset POR

 

Reset Peripheral

 

Reset COP

 

Cont Sys Clk In

 

Bscan Enable

Power Modes: Run, Wait, Pre-Stop, Stop

 

 

 

 

 

P5STOP

 

 

 

 

 

 

 

 

Cont Sys Clk In

 

P5WAIT

 

 

Power Mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OSC_LOPWR

 

Int Pending

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTDEBREQ/DE

 

 

 

Control

 

 

 

 

PLL Shutdown

 

 

 

 

 

 

 

 

 

 

 

 

OMR6_SD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*Cont SYS_CLK_IN is a synthesized clock tree fed by CLK_SYS Cont output of SIM

Figure 4-1. System Integration Module

System Integration Module (SIM), Rev. 4

Freescale Semiconductor

4-5

-packaged product lines and part numbers indicated here currently are not

2010: MC13892

Commission, BGA

prior to September

order from the United States International Trade Freescale for import or sale in the United States

of an from

Because

available

Signal Description

4.4 Signal Description

A description of the System Integration Module (SIM) signals is listed in Tables 4-1 through

Tables 4-6.

4.4.1 SIM Interface Signals

Table 4-1. IPBus Signals

 

Name

 

Type

Clock Domain

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_IPB

 

Input

Peripheral bus clock

 

RD_DATA_Z

 

Output

CLK_IPB

Read data (tri-stateable)

 

 

 

 

 

 

 

WR_DATA

 

Input

CLK_IPB

Write data

 

 

 

 

 

 

 

ADDR

 

Input

CLK_IPB

R/W address (two LSBs of IPBus Address)

 

 

 

 

 

 

 

RWB

 

Input

CLK_IPB

Write enable (active low)

 

 

 

 

 

 

 

 

 

Input

CLK_IPB

Module enable (active low)

 

MODULE_EN

 

 

 

 

 

 

Table 4-2. Reset Generator Inputs/Outputs

 

 

 

 

 

Name

Type

Clock Domain

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

CLK_SYS_CONT

Synchronized and extended reset to core

RST_CORE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

CLK_SYS_CONT

Synchronized and extended reset to general peripheral

RST_PERIPH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

logic

 

 

 

 

 

 

 

 

 

 

Output

CLK_OSC

Synchronized and extended reset to CGM module

 

 

 

RST_CGM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Reset request from external reset pin

 

 

 

 

 

RST_PIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Reset request from power-on reset module

 

 

 

RST_POR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Reset request from COP module

 

 

 

RST_COP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

56852 Digital Signal Controller User Manual, Rev. 4

4-6

Freescale Semiconductor

-packaged product lines and part numbers indicated here currently are not

2010: MC13892

Commission, BGA

prior to September

order from the United States International Trade Freescale for import or sale in the United States

of an from

Because

available

Signal Description

Table 4-3. Register Inputs/Outputs

Name

Type

Clock Domain

 

 

Function

 

 

 

 

 

 

 

 

MODE_CBA[2:0]

Input

From [15:13] input pads, captured at reset in SIM control

register to indicate software boot mode

 

 

 

 

 

 

 

PRAM_DBL

Output

CLK_IPB

Redirect program RAM accesses to external memory IF

 

 

 

 

DRAM_DBL

Output

CLK_IPB

Redirect data RAM accesses to external memory IF

 

 

 

 

STOP_DBL

Output

CLK_IPB

Direct the core to disable the Stop instruction

 

 

 

 

WAIT_DBL

Output

CLK_IPB

Direct the core to disable the Wait instruction

 

 

 

 

CFG_CO

Output

CLK_IPB

Replace CLKOUT output with A[20] output

 

 

 

 

 

 

CFG_A19

Output

CLK_IPB

Replace A[19] output with

 

output

CS3

 

 

 

 

CFG_A18

Output

CLK_IPB

Replace A[18] output withTIO[1] output

 

 

 

 

CFG_A17

Output

CLK_IPB

Replace A[17] output with TIO[0] output

 

 

 

 

CFG_SCK

Output

CLK_IPB

Replace SCK output with STCK output

 

 

 

 

 

 

CFG_SSB

Output

CLK_IPB

Replace

 

output with STFS output

SS

 

 

 

 

CFG_MISO

Output

CLK_IPB

Replace MISO output with SRCK output

 

 

 

 

CFG_MOSI

Output

CLK_IPB

Replace MOSI output with SRFS output

 

 

 

 

 

 

 

 

Table 4-4. Power Mode Control Inputs/Outputs

Name

Type

Clock Domain

 

 

Function

 

 

 

 

 

 

 

 

STOPMD

Output

CLK_SYS_CONT

Indicates SIM is in Stop mode

 

 

 

 

WAITMD

Output

CLK_SYS_CONT

Indicates SIM is in Wait mode

 

 

 

 

RUNMD

Output

CLK_SYS_CONT

Indicates SIM is in Run mode

 

 

 

 

OSC_LOPWR

Output

CLK_SYS_CONT

Puts oscillator into Low Power mode configuration during

 

 

 

 

 

Stop mode

PLL_SHUTDOWN

Output

CLK_SYS_CONT

Shuts down PLL and puts it into Bypass mode when

 

 

 

 

 

entering Stop mode

P5STOP

Input

CLK_SYS_CONT

Input from the core indicating Stop instruction executed

 

 

 

 

P5WAIT

Input

CLK_SYS_CONT

Input from the core indicating Wait instruction executed

 

 

 

 

INT_PEND

Input

CLK_SYS_CONT

Input from INTC indicating interrupt is pending

 

 

 

 

JTDEBREQ

Input

CLK_SYS_CONT

Input from core indicating a JTAG Debug mode request

 

 

 

 

 

 

 

 

 

 

 

Input

CLK_SYS_CONT

Input from

 

input pad used to enter OnCE Debug mode

 

DE

DE

 

 

 

 

OMR6_SD

Input

CLK_SYS_CONT

From core omr6 register to enable fast Stop mode recovery

 

 

 

 

 

 

BSCAN_EBL

Input

From external TAP controller indicating Boundary Scan

mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System Integration Module (SIM), Rev. 4

Freescale Semiconductor

4-7

-packaged product lines and part numbers indicated here currently are not

2010: MC13892

Commission, BGA

prior to September

order from the United States International Trade Freescale for import or sale in the United States

of an from

Because

available

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