
- •Preface
- •About This Manual
- •Audience
- •Manual Organization
- •Suggested Reading
- •Manual Conventions
- •1.1 Introduction
- •1.2 56800E Core Description
- •1.3 56852 Architectural Overview
- •1.4 System Bus Controller
- •1.5 56852 Memory
- •1.6 56852 Peripheral Blocks
- •2.1 Introduction
- •2.2 Features
- •2.3 Signal and Package Information
- •3.1 Introduction
- •3.2 Program Boot ROM
- •3.3 Memory Map
- •4.1 Introduction
- •4.2 Features
- •4.3 SIM Block Diagram
- •4.4 Signal Description
- •4.5 Module Memory Map
- •4.6 Register Descriptions (SYS_BASE = $1FFF08)
- •4.7 Implementation
- •4.8 Generated Clocks
- •4.9 Generated Resets
- •4.10 Power Mode Controls
- •5.1 Introduction
- •5.2 Features
- •5.3 Functional Description
- •5.4 Block Diagram
- •5.5 Module Memory Map
- •5.6 Register Descriptions (EMI_BASE = $1FFE40)
- •5.7 Timing Specifications
- •5.8 Clocks
- •5.9 Interrupts
- •5.10 Resets
- •6.1 Introduction
- •6.2 OSC (Oscillator) Circuit Detail
- •6.3 Phase Locked Loop (PLL) Circuit Detail
- •6.4 CGM Functional Detail
- •6.5 Module Memory Map
- •6.6 Register Descriptions (CGM_BASE = $1FFF10)
- •6.7 OCCS Resets
- •6.8 OCCS Interrupts
- •7.1 Introduction
- •7.2 Features
- •7.3 Block Diagram
- •7.4 Method of Operation
- •7.5 Computer Operating Properly (COP) Module
- •7.6 Operating Modes
- •7.7 Block Diagram
- •7.8 Module Memory Map
- •7.9 Register Descriptions (COP_BASE = $1FFFD0)
- •7.10 Clocks
- •7.11 Resets
- •7.12 Interrupts
- •8.1 Introduction
- •8.2 Features
- •8.3 ITCN Module Signal Description
- •8.4 Block Diagram
- •8.5 Functional Description
- •8.6 Operating Modes
- •8.7 Wait and Stop Modes Operations
- •8.8 Module Memory Map
- •8.9 Register Descriptions (ITCN_BASE = $1FFF20)
- •8.10 Resets
- •8.11 Interrupts
- •9.1 Introduction
- •9.2 Features
- •9.3 Block Diagram
- •9.4 Signal Descriptions
- •9.5 Functional Description
- •9.6 Low Power Modes
- •9.7 Module Memory Map
- •9.8 Register Descriptions (SCI_BASE = $1FFFE0)
- •9.9 Clocks
- •9.10 Resets
- •9.11 Interrupts
- •10.1 Introduction
- •10.2 Features
- •10.3 SPI Block Diagram
- •10.4 Signal Descriptions
- •10.5 External I/O Signals
- •10.6 Operating Modes
- •10.7 Transmission Formats
- •10.8 Transmission Data
- •10.9 Error Conditions
- •10.10 Module Memory Map
- •10.11 Registers Descriptions (SPI_BASE = $1FFFE8)
- •10.12 Resets
- •10.13 Interrupts
- •11.1 Introduction
- •11.2 Features
- •11.3 Signal Descriptions
- •11.4 Block Diagram
- •11.5 ISSI Configurations
- •11.6 Module Memory Map
- •11.7 Register Descriptions (ISSI_BASE = $1FFE20)
- •11.8 ISSI Operating Modes
- •11.9 Clocks
- •11.10 Clock Operation Description
- •11.11 Resets
- •11.12 Interrupts
- •11.13 User Notes
- •12.1 Introduction
- •12.2 Features
- •12.3 Operating Modes
- •12.4 Block Diagram
- •12.5 Signal Description
- •12.6 Functional Description
- •12.7 Counting Modes Definitions
- •12.8 Module Memory Map
- •12.9 Register Descriptions (TMR_BASE = $1FFE80)
- •12.10 Resets
- •12.11 Interrupts
- •13.1 Introduction
- •13.2 Features
- •13.3 GPIO Block Diagram
- •13.4 Functional Description
- •13.5 Modes of Operation
- •13.6 GPIO Configurations
- •13.7 Module Memory Maps
- •13.8 Register Descriptions
- •13.9 Data Register Access
- •13.10 Resets
- •13.11 Interrupts
- •14.1 Introduction
- •14.2 Features
- •14.3 Master Test Access Port (TAP)
- •14.4 TAP Block Diagram
- •14.5 JTAG Port Architecture
- •14.6 JTAG Bypass Register (JTAGBR)
- •14.7 JTAG Boundary Scan Register (BSR)
- •14.8 TAP Controller
- •14.9 56852 Restrictions
- •B.1 Introduction
- •B.2 Programmer’s Sheets

Features
4.1 Introduction
The System Integration Module (SIM) is responsible for system control functions listed below:
•Clock generation
•Reset generation
•Power mode control
•Boot mode control
•Memory map control
•Integrated Circuit (IC) configuration control
•External I/O configuration control
•Software control registers
4.2Features
The SIM module provides these listed qualities:
•Four system bus clocks with pipeline hold-off support
–Data RAM clock with hold-off control
–IPBus Interface clock with hold-off control
–Core system clock
–General purpose clock (both standard and inverted versions)
•Three system clocks for non-pipelined interfaces
–PCLK clock for core
–NCLK clock for core
–A continuously running system clock
•A peripheral bus (IPBus) clock, both standard and inverted versions
•An external clock output with disable
•A peripheral bus clock phase indicator
•Three power modes to control power utilization:
–Stop mode shuts down core, system clocks, and peripheral bug clocks. Stop mode entry can optionally disable PLL and Oscillator (lowest power vs. fast restart).
–Wait mode shuts down the core, and unnecessary system clock operation while peripherals continue to operate.
|
System Integration Module (SIM), Rev. 4 |
Freescale Semiconductor |
4-3 |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
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Because |
available |

Features
–Run mode supports full part operation
•Controls to enable/disable the core Wait and Stop instructions
•32-cycle extended synchronous resets for CGM, the core, and other system blocks
•Software initiated reset
•Controls to redirect internal data and/or program RAM accesses to the external memory interface
•Software Boot mode control register (initialized at any reset except COP reset from external pads)
•A hold-off output to coordinate the system and peripheral buses
•Two 16-bit software control registers reset only by a power-on reset usable for general purpose software control
•Eight bits to control external I/O configurations
•Features to support testing of the SIM and the IC
–Scan test support
–JTAG boundary scan
–Peripheral Broadside Test mode
|
56852 Digital Signal Controller User Manual, Rev. 4 |
4-4 |
Freescale Semiconductor |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

SIM Block Diagram
4.3 SIM Block Diagram
The System Integration Module (SIM) is depicted in Table 4-1.
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CFG_* |
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Configuration Register |
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Software Control Reg 1 |
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IPBus |
Bus |
Software Control Reg 2 |
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Interface |
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Modes A, B, C |
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SIM Control Register |
P/D RAM Disable |
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Stop/Wait Disable |
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IPBus Slow Write |
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Master CLK |
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Pipelined Sys Clks |
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Scan CLK |
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Other Sys Clks |
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IPBB Hold-Off |
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Clock Generator |
56800E Clks |
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XRAM Hold-Off |
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Core Stall |
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Periph Bus Clk |
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Periph Bus Phase |
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CLKOUT Disable |
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Hold-Off |
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NCLK Enable |
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Cont Sys Clk* |
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Internal Clk |
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POR Disable |
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Reset POR |
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Reset Internal |
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Reset SW |
Reset Generator |
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Reset Core |
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Reset Pin |
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Reset POR |
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Reset Peripheral |
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Reset COP |
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Cont Sys Clk In |
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Bscan Enable |
Power Modes: Run, Wait, Pre-Stop, Stop |
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P5STOP |
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Cont Sys Clk In |
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P5WAIT |
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Power Mode |
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OSC_LOPWR |
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Int Pending |
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JTDEBREQ/DE |
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Control |
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PLL Shutdown |
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OMR6_SD |
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*Cont SYS_CLK_IN is a synthesized clock tree fed by CLK_SYS Cont output of SIM
Figure 4-1. System Integration Module
System Integration Module (SIM), Rev. 4
Freescale Semiconductor |
4-5 |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

Signal Description
4.4 Signal Description
A description of the System Integration Module (SIM) signals is listed in Tables 4-1 through
Tables 4-6.
4.4.1 SIM Interface Signals
Table 4-1. IPBus Signals
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Name |
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Type |
Clock Domain |
Function |
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CLK_IPB |
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Input |
— |
Peripheral bus clock |
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RD_DATA_Z |
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Output |
CLK_IPB |
Read data (tri-stateable) |
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WR_DATA |
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Input |
CLK_IPB |
Write data |
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ADDR |
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Input |
CLK_IPB |
R/W address (two LSBs of IPBus Address) |
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RWB |
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Input |
CLK_IPB |
Write enable (active low) |
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Input |
CLK_IPB |
Module enable (active low) |
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MODULE_EN |
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Table 4-2. Reset Generator Inputs/Outputs
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Name |
Type |
Clock Domain |
Function |
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Output |
CLK_SYS_CONT |
Synchronized and extended reset to core |
RST_CORE |
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Output |
CLK_SYS_CONT |
Synchronized and extended reset to general peripheral |
RST_PERIPH |
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logic |
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Output |
CLK_OSC |
Synchronized and extended reset to CGM module |
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RST_CGM |
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Input |
— |
Reset request from external reset pin |
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RST_PIN |
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Input |
— |
Reset request from power-on reset module |
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RST_POR |
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Input |
— |
Reset request from COP module |
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RST_COP |
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56852 Digital Signal Controller User Manual, Rev. 4 |
4-6 |
Freescale Semiconductor |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

Signal Description
Table 4-3. Register Inputs/Outputs
Name |
Type |
Clock Domain |
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Function |
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MODE_CBA[2:0] |
Input |
— |
From [15:13] input pads, captured at reset in SIM control |
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register to indicate software boot mode |
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PRAM_DBL |
Output |
CLK_IPB |
Redirect program RAM accesses to external memory IF |
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DRAM_DBL |
Output |
CLK_IPB |
Redirect data RAM accesses to external memory IF |
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STOP_DBL |
Output |
CLK_IPB |
Direct the core to disable the Stop instruction |
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WAIT_DBL |
Output |
CLK_IPB |
Direct the core to disable the Wait instruction |
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CFG_CO |
Output |
CLK_IPB |
Replace CLKOUT output with A[20] output |
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CFG_A19 |
Output |
CLK_IPB |
Replace A[19] output with |
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CS3 |
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CFG_A18 |
Output |
CLK_IPB |
Replace A[18] output withTIO[1] output |
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CFG_A17 |
Output |
CLK_IPB |
Replace A[17] output with TIO[0] output |
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CFG_SCK |
Output |
CLK_IPB |
Replace SCK output with STCK output |
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CFG_SSB |
Output |
CLK_IPB |
Replace |
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SS |
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CFG_MISO |
Output |
CLK_IPB |
Replace MISO output with SRCK output |
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CFG_MOSI |
Output |
CLK_IPB |
Replace MOSI output with SRFS output |
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Table 4-4. Power Mode Control Inputs/Outputs
Name |
Type |
Clock Domain |
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Function |
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STOPMD |
Output |
CLK_SYS_CONT |
Indicates SIM is in Stop mode |
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WAITMD |
Output |
CLK_SYS_CONT |
Indicates SIM is in Wait mode |
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RUNMD |
Output |
CLK_SYS_CONT |
Indicates SIM is in Run mode |
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OSC_LOPWR |
Output |
CLK_SYS_CONT |
Puts oscillator into Low Power mode configuration during |
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Stop mode |
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PLL_SHUTDOWN |
Output |
CLK_SYS_CONT |
Shuts down PLL and puts it into Bypass mode when |
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entering Stop mode |
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P5STOP |
Input |
CLK_SYS_CONT |
Input from the core indicating Stop instruction executed |
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P5WAIT |
Input |
CLK_SYS_CONT |
Input from the core indicating Wait instruction executed |
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INT_PEND |
Input |
CLK_SYS_CONT |
Input from INTC indicating interrupt is pending |
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JTDEBREQ |
Input |
CLK_SYS_CONT |
Input from core indicating a JTAG Debug mode request |
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Input |
CLK_SYS_CONT |
Input from |
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input pad used to enter OnCE Debug mode |
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DE |
DE |
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OMR6_SD |
Input |
CLK_SYS_CONT |
From core omr6 register to enable fast Stop mode recovery |
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BSCAN_EBL |
Input |
— |
From external TAP controller indicating Boundary Scan |
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mode |
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|
System Integration Module (SIM), Rev. 4 |
Freescale Semiconductor |
4-7 |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |