TAP Controller

14.8 TAP Controller

The TAP Controller is a synchronous 16-bit finite state machine illustrated in Figure 14-7. It responds to changes at the TMS and TCK pins. Transitions from one state to another will occur on the rising edge of TCK. The value shown adjacent to each state transition represents the signal present on TMS at the time of a rising edge of TCK.

The TDO pin will remain in the high impedance state except during the Shift-DR and Shift-IR TAP Controller states. In these controller states, TDO will update on the falling edge of TCK. TDI is sampled on the rising edge of TCK.

The TAP Controller will execute the last instruction decoded until a new instruction is entered at the Update-IR state, or Test-Logic-Reset is entered.

Test-Logic-Reset F

Figure 14-7. TAP Controller State Diagram

TAP Controller

The TAP Controller will execute the last instruction decoded until a new instruction is entered at the Update-IR state, or Test-Logic-Reset is entered.

There are two paths through the 16-state machine. The shift-IR-scan path captures and loads JTAG instructions into the JTAGIR. The shift-DR-scan path captures and loads data into the other JTAG registers. The TAP Controller executes the last instruction decoded until a new instruction is entered at the update-IR state, or until the test-logic-reset state is entered. When using the JTAG port to access EOnCE module registers, follow these four steps:

1.Enable the TLM by shifting the TLM_SEL instruction into the JTAGIR.

2.When selected, the TLM must enable the 56800E TAP by shifting in the appropriate value into the TLM Register.

3.When the 56800E TAP is selected, the EOnCE module is selected by shifting the ENABLE_EOnCE instruction.

4.The EOnCE module registers and commands are read and written through the JTAG pins using the shift-DR-scan path.

Asserting the JTAG’s TRST pin asynchronously forces the JTAG state machine into the test-logic-reset state.

14.8.1 Operation

All state transitions of the TAP Controller occur based on the value of TMS at the time of a rising edge of TCK. Actions of the instructions occur on the falling edge of TCK in each controller state illustrated in Figure 14-7.

14.8.1.1 Test Logic Reset (pstate = F)

During Test-Logic-Reset all JTAG test logic is disabled so the chip can operate in a normal mode. This is achieved by initializing the Instruction Register (IR) with the IDCODE instruction. By holding TMS high for five rising edges of TCK, the device will always remain in Test-Logic-Reset no matter what state the TAP Controller was in previously.

14.8.1.2 Run-Test-Idle (pstate = C)

Run-Test-Idle is a controller state between scan operations. EOnCE entered, the controller will remain in the Run-Test-Idle mode as long as TMS is held low. When TMS is high and a rising edge of TCK occurs, the controller moves to the Select-DR state.

TAP Controller

14.8.1.3 Select Data Register (pstate = 7)

The Select-DR state is a temporary state. In this state, all Test Data Registers selected by the current instruction retains their previous states. If TMS is held low and a rising edge of TCK occurs when the controller is in this state, the controller moves into the Capture-DR state and a scan sequence for the selected Test Data Register is initiated. If TMS is held high and a rising edge of TCK occurs, the controller moves to the Select-IR state.

14.8.1.4 Select Instruction Register (pstate = 4)

The Select-IR state is a temporary state. In this state, all Test Data Registers selected by a current instruction retain their previous states. If TMS is held low and a rising edge of TCK occurs when the controller is in this state, the controller moves into the Capture-IR state and a scan sequence for the Instruction Register is initiated. If TMS is held high and a rising edge of TCK occurs, the controller moves to the Test-Logic-Reset state.

14.8.1.5 Capture Data Register (pstate = 6)

In this controller state, data may be parallel loaded into test registers selected by the current instruction on the rising edge of TCK. If a test data register selected by the current instruction does not have a parallel input, the register retains its previous value.

14.8.1.6 Shift Data Register (pstate = 2)

In this controller state, the Test Data Register is connected between TDI and TDO. This data is then shifted one stage towards its serial output on each rising edge of TCK. The TAP Controller will remain in this state while TMS is held at a low. When a one is applied to TMS and a positive edge of TCK occurs, the controller will move to the Exit1-DR state.

14.8.1.7 Exit1 Data Register (pstate = 1)

This is a temporary controller state. If TMS is held high, and a rising edge is applied to TCK while in this state, it causes the controller to advance to the Update-DR state. This terminates the scanning process.

14.8.1.8 Pause Data Register (pstate = 3)

This controller state allows shifting of the Test Data Register in the serial path between TDI and TDO to be temporarily halted. All test data registers selected by the current instruction retain their previous state unchanged. The controller remains in this state while TMS is held low. When TMS goes high and a rising edge is applied to TCK, the controller advances to the Exit2-DR state.

TAP Controller

14.8.1.9 Exit2 Data Register (pstate = 0)

This is a temporary controller state. If TMS is held high, and a rising edge is applied to TCK while it is in this state, the scanning process terminates and the TAP Controller advances to the Update-DR state. If TMS is held low and a rising edge of TCK occurs, the controller advances to the Shift-DR state.

14.8.1.10 Update Data Register (pstate = 5)

All boundary scan registers contain a two stage data register. It isolates the shifting and capturing of data on the peripheral from what is applied to internal logic during scan mode. This register is the second stage, or parallel output, and it is used to apply a stimulus to internal logic. Data is latched on the parallel output of these Test Data Registers from the Shift Register path on the falling edge of TCK in the Update-DR state. On a rising edge of TCK, the controller advances to the Select_DR state if TMS is held high or the Run-Test-Idle state If TMS is held low.

14.8.1.11 Capture Instruction Register (pstate = E)

When the TAP Controller is in this state and a rising edge of TCK occurs, the controller advances to the Exit1-IR state if TMS is held at a one or the Shift-IR state if TMS is held at a zero.

14.8.1.12 Shift Instruction Register (pstate = A)

In this controller state, the Shift Register contained in the Instruction Register (IR) is connected between TDI and TDO and shifts data one stage towards it’s serial output on each rising edge of TCK. When the TAP Controller is in this state and a rising edge of TCK occurs, the controller advances to the Exit1-IR state if TMS is held at a one or remains in the Shift-IR state if TMS is held at a zero.

14.8.1.13 Exit1 Instruction Register (pstate = 9)

This is a temporary controller state. If TMS is held high, and a rising edge is applied to TCK while in this state causes the controller to advance to the Update-IR state. This terminates the scanning process. If TMS is held low and a rising edge of TCK occurs the controller advances to the Pause-IR state.

14.8.1.14 Pause Instruction Register (pstate = B)

This controller state allows shifting of the Instruction Register (IR) in the serial path between TDI and TDO to be temporarily halted. All Test Data Registers selected by the current instruction retain their previous state unchanged. The controller remains in this state while TMS is held low. When TMS goes high and a rising edge is applied to TCK, the controller advances to the Exit2-IR state.