
- •Preface
- •About This Manual
- •Audience
- •Manual Organization
- •Suggested Reading
- •Manual Conventions
- •1.1 Introduction
- •1.2 56800E Core Description
- •1.3 56852 Architectural Overview
- •1.4 System Bus Controller
- •1.5 56852 Memory
- •1.6 56852 Peripheral Blocks
- •2.1 Introduction
- •2.2 Features
- •2.3 Signal and Package Information
- •3.1 Introduction
- •3.2 Program Boot ROM
- •3.3 Memory Map
- •4.1 Introduction
- •4.2 Features
- •4.3 SIM Block Diagram
- •4.4 Signal Description
- •4.5 Module Memory Map
- •4.6 Register Descriptions (SYS_BASE = $1FFF08)
- •4.7 Implementation
- •4.8 Generated Clocks
- •4.9 Generated Resets
- •4.10 Power Mode Controls
- •5.1 Introduction
- •5.2 Features
- •5.3 Functional Description
- •5.4 Block Diagram
- •5.5 Module Memory Map
- •5.6 Register Descriptions (EMI_BASE = $1FFE40)
- •5.7 Timing Specifications
- •5.8 Clocks
- •5.9 Interrupts
- •5.10 Resets
- •6.1 Introduction
- •6.2 OSC (Oscillator) Circuit Detail
- •6.3 Phase Locked Loop (PLL) Circuit Detail
- •6.4 CGM Functional Detail
- •6.5 Module Memory Map
- •6.6 Register Descriptions (CGM_BASE = $1FFF10)
- •6.7 OCCS Resets
- •6.8 OCCS Interrupts
- •7.1 Introduction
- •7.2 Features
- •7.3 Block Diagram
- •7.4 Method of Operation
- •7.5 Computer Operating Properly (COP) Module
- •7.6 Operating Modes
- •7.7 Block Diagram
- •7.8 Module Memory Map
- •7.9 Register Descriptions (COP_BASE = $1FFFD0)
- •7.10 Clocks
- •7.11 Resets
- •7.12 Interrupts
- •8.1 Introduction
- •8.2 Features
- •8.3 ITCN Module Signal Description
- •8.4 Block Diagram
- •8.5 Functional Description
- •8.6 Operating Modes
- •8.7 Wait and Stop Modes Operations
- •8.8 Module Memory Map
- •8.9 Register Descriptions (ITCN_BASE = $1FFF20)
- •8.10 Resets
- •8.11 Interrupts
- •9.1 Introduction
- •9.2 Features
- •9.3 Block Diagram
- •9.4 Signal Descriptions
- •9.5 Functional Description
- •9.6 Low Power Modes
- •9.7 Module Memory Map
- •9.8 Register Descriptions (SCI_BASE = $1FFFE0)
- •9.9 Clocks
- •9.10 Resets
- •9.11 Interrupts
- •10.1 Introduction
- •10.2 Features
- •10.3 SPI Block Diagram
- •10.4 Signal Descriptions
- •10.5 External I/O Signals
- •10.6 Operating Modes
- •10.7 Transmission Formats
- •10.8 Transmission Data
- •10.9 Error Conditions
- •10.10 Module Memory Map
- •10.11 Registers Descriptions (SPI_BASE = $1FFFE8)
- •10.12 Resets
- •10.13 Interrupts
- •11.1 Introduction
- •11.2 Features
- •11.3 Signal Descriptions
- •11.4 Block Diagram
- •11.5 ISSI Configurations
- •11.6 Module Memory Map
- •11.7 Register Descriptions (ISSI_BASE = $1FFE20)
- •11.8 ISSI Operating Modes
- •11.9 Clocks
- •11.10 Clock Operation Description
- •11.11 Resets
- •11.12 Interrupts
- •11.13 User Notes
- •12.1 Introduction
- •12.2 Features
- •12.3 Operating Modes
- •12.4 Block Diagram
- •12.5 Signal Description
- •12.6 Functional Description
- •12.7 Counting Modes Definitions
- •12.8 Module Memory Map
- •12.9 Register Descriptions (TMR_BASE = $1FFE80)
- •12.10 Resets
- •12.11 Interrupts
- •13.1 Introduction
- •13.2 Features
- •13.3 GPIO Block Diagram
- •13.4 Functional Description
- •13.5 Modes of Operation
- •13.6 GPIO Configurations
- •13.7 Module Memory Maps
- •13.8 Register Descriptions
- •13.9 Data Register Access
- •13.10 Resets
- •13.11 Interrupts
- •14.1 Introduction
- •14.2 Features
- •14.3 Master Test Access Port (TAP)
- •14.4 TAP Block Diagram
- •14.5 JTAG Port Architecture
- •14.6 JTAG Bypass Register (JTAGBR)
- •14.7 JTAG Boundary Scan Register (BSR)
- •14.8 TAP Controller
- •14.9 56852 Restrictions
- •B.1 Introduction
- •B.2 Programmer’s Sheets

JTAG Boundary Scan Register (BSR)
Table 14-4. Device ID Register Bit Assignment
Bit No. |
Code Use |
56852 Values |
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31–28 |
Version Number |
0000 (For initial version only—these bits may vary) |
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27–22 |
Freescale Design Center ID |
00 0111 |
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21–12 |
Family and part ID |
11 0101 0100 |
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11-1 |
Freescale Manufacturer ID |
000 0000 1110 |
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0 |
IEEE Requirement |
Always 1 |
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14.6 JTAG Bypass Register (JTAGBR)
The JTAG bypass register is a one-bit register used to provide a simple, direct path from the TDI pin to the TDO pin. This is useful in boundary scan applications where many chips are serially connected in a daisy-chain. Individual DSCs, or other devices, can be programmed with the BYPASS instruction so individually they become pass-through devices during testing. This allows testing of a specific chip, while still having all of the chips connected through the JTAG ports.
IR = $6, $7, $FF
Read/Write
Reset 0
Figure 14-5. JTAG Bypass Register (JTAGBR)
14.7 JTAG Boundary Scan Register (BSR)
The JTAG Boundary Scan Register (BSR) is configured as described in Figure 14-6. This register is enabled via the JTAG Master TAP by issuing the EXTEST, or SAMPLE_PRELOAD instructions enabling the boundary scan registers between TDI and TDO. Boundary Scan Register cell number one is connected to TDO making it the first data bit shifted into TDI. It is the first bit shifted out of TDO when loading and unloading the boundary scan chain. For the most current BSDL files, please refer to www.freescale.com. Figure 14-6 illustrates the register, while Table 14-5 provides the contents of the BSR for the 56852.
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IR = $0, $1, $3 |
337 |
336 |
335 |
334 |
333 |
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Bits 332 through 5 |
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4 |
3 |
2 |
1 |
0 |
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Read-Only |
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Figure 14-6. Boundary Scan Register (BSR) |
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JTAG Port, Rev. 4 |
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Freescale Semiconductor |
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14-11 |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

JTAG Boundary Scan Register (BSR)
Table 14-5. BSR Contents for 56852
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Bit Number |
Pin/Bit Name |
Pin Type |
BSR Cell |
Pin Number |
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0 |
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Input |
BC_1 |
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IRQA |
A1 |
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1 |
Pull-up |
BC_1 |
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2 |
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Input |
BC_1 |
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IRQB |
C2 |
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3 |
Pull-up |
BC_1 |
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4 |
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Input/Output |
BC_7 |
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D2 |
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5 |
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CS0 |
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Pull-up |
BC_1 |
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6 |
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Enable |
BC_2a |
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7 |
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Input/Output |
BC_7 |
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8 |
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CS1 |
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Pull-up |
BC_1 |
D3 |
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9 |
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Enable |
BC_2a |
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10 |
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Input/Output |
BC_7 |
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C3 |
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11 |
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CS2 |
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Pull-up |
BC_1 |
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12 |
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Enable |
BC_2a |
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13 |
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Input/Output |
BC_7 |
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14 |
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RD |
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Pull-up |
BC_1 |
E2 |
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15 |
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Enable |
BC_2a |
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16 |
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Input/Output |
BC_7 |
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E3 |
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17 |
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WR |
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Pull-up |
BC_1 |
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18 |
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Enable |
BC_2a |
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19 |
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Input/Output |
BC_7 |
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20 |
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A0 |
Pull-up |
BC_1 |
E4 |
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21 |
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Enable |
BC_2a |
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22 |
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Input/Output |
BC_7 |
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A1 |
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F2 |
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23 |
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Pull-up |
BC_1 |
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24 |
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Enable |
BC_2a |
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25 |
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Input/Output |
BC_7 |
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26 |
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A2 |
Pull-up |
BC_1 |
F3 |
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27 |
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Enable |
BC_2a |
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28 |
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Input/Output |
BC_7 |
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A3 |
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F4 |
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29 |
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Pull-up |
BC_1 |
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30 |
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Enable |
BC_2a |
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31 |
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Input/Output |
BC_7 |
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32 |
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A4 |
Pull-up |
BC_1 |
F1 |
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33 |
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Enable |
BC_2a |
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34 |
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Input/Output |
BC_7 |
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A5 |
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G3 |
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35 |
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Pull-up |
BC_1 |
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36 |
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Enable |
BC_2a |
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56852 Digital Signal Controller User Manual, Rev. 4 |
|||||||||||||
14-12 |
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|
Freescale Semiconductor |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

JTAG Boundary Scan Register (BSR)
Table 14-5. BSR Contents for 56852 (Continued)
Bit Number |
Pin/Bit Name |
Pin Type |
BSR Cell |
Pin Number |
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37 |
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Input/Output |
BC_7 |
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38 |
A6 |
Pull-up |
BC_1 |
G2 |
39 |
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Enable |
BC_2a |
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40 |
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Input/Output |
BC_7 |
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A7 |
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J1 |
41 |
Pull-up |
BC_1 |
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42 |
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Enable |
BC_2a |
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43 |
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Input/Output |
BC_7 |
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44 |
A8 |
Pull-up |
BC_1 |
H2 |
45 |
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Enable |
BC_2a |
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46 |
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Input/Output |
BC_7 |
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A9 |
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H3 |
47 |
Pull-up |
BC_1 |
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48 |
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Enable |
BC_2a |
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49 |
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Input/Output |
BC_7 |
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50 |
A10 |
Pull-up |
BC_1 |
J2 |
51 |
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Enable |
BC_2a |
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52 |
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Input/Output |
BC_7 |
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A11 |
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H4 |
53 |
Pull-up |
BC_1 |
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54 |
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Enable |
BC_2a |
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55 |
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Input/Output |
BC_7 |
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56 |
A12 |
Pull-up |
BC_1 |
G4 |
57 |
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Enable |
BC_2a |
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58 |
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Input/Output |
BC_7 |
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A13 |
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J3 |
59 |
Pull-up |
BC_1 |
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60 |
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Enable |
BC_2a |
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61 |
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Input/Output |
BC_7 |
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62 |
A14 |
Pull-up |
BC_1 |
F5 |
63 |
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Enable |
BC_2a |
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64 |
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Input/Output |
BC_7 |
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A15 |
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H5 |
65 |
Pull-up |
BC_1 |
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66 |
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Enable |
BC_2a |
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67 |
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Input/Output |
BC_7 |
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68 |
A16 |
Pull-up |
BC_1 |
E5 |
69 |
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Enable |
BC_2a |
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70 |
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Input/Output |
BC_7 |
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A17 |
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F6 |
71 |
Pull-up |
BC_1 |
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72 |
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Enable |
BC_2a |
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73 |
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Input/Output |
BC_7 |
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74 |
A18 |
Pull-up |
BC_1 |
G5 |
75 |
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Enable |
BC_2a |
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|
JTAG Port, Rev. 4 |
Freescale Semiconductor |
14-13 |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

JTAG Boundary Scan Register (BSR)
Table 14-5. BSR Contents for 56852 (Continued)
|
Bit Number |
Pin/Bit Name |
Pin Type |
BSR Cell |
Pin Number |
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76 |
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Input/Output |
BC_7 |
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A19 |
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B8 |
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77 |
Pull-up |
BC_1 |
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78 |
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Enable |
BC_2a |
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79 |
A20 |
Input/Output |
BC_7 |
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80 |
Pull-up |
BC_1 |
J8 |
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(CLK0) |
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81 |
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Enable |
BC_2a |
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82 |
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Input/Output |
BC_7 |
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D0 |
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G7 |
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83 |
Pull-up |
BC_1 |
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84 |
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Enable |
BC_2a |
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85 |
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Input/Output |
BC_7 |
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86 |
D1 |
Pull-up |
BC_1 |
H7 |
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87 |
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Enable |
BC_2a |
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88 |
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Input/Output |
BC_7 |
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D2 |
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H8 |
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89 |
Pull-up |
BC_1 |
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90 |
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Enable |
BC_2a |
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91 |
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Input/Output |
BC_7 |
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92 |
D3 |
Pull-up |
BC_1 |
G8 |
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93 |
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Enable |
BC_2a |
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94 |
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Input/Output |
BC_7 |
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D4 |
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H9 |
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95 |
Pull-up |
BC_1 |
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96 |
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Enable |
BC_2a |
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97 |
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Input/Output |
BC_7 |
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98 |
D5 |
Pull-up |
BC_1 |
E8 |
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99 |
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Enable |
BC_2a |
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100 |
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Input/Output |
BC_7 |
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D6 |
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F7 |
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101 |
Pull-up |
BC_1 |
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102 |
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Enable |
BC_2a |
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103 |
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Input/Output |
BC_7 |
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104 |
D7 |
Pull-up |
BC_1 |
G6 |
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105 |
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Enable |
BC_2a |
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106 |
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Input/Output |
BC_7 |
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D8 |
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E8 |
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107 |
Pull-up |
BC_1 |
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108 |
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Enable |
BC_2a |
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109 |
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Input/Output |
BC_7 |
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110 |
D9 |
Pull-up |
BC_1 |
E7 |
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111 |
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Enable |
BC_2a |
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112 |
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Input/Output |
BC_7 |
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D10 |
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E6 |
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113 |
Pull-up |
BC_1 |
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114 |
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Enable |
BC_2a |
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56852 Digital Signal Controller User Manual, Rev. 4 |
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14-14 |
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Freescale Semiconductor |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

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JTAG Boundary Scan Register (BSR) |
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Table 14-5. BSR Contents for 56852 (Continued) |
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Bit Number |
Pin/Bit Name |
Pin Type |
BSR Cell |
Pin Number |
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115 |
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Input/Output |
BC_7 |
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116 |
D11 |
Pull-up |
BC_1 |
D8 |
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117 |
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Enable |
BC_2a |
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118 |
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Input/Output |
BC_7 |
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D12 |
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D7 |
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119 |
Pull-up |
BC_1 |
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120 |
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Enable |
BC_2a |
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121 |
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Input/Output |
BC_7 |
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122 |
D13 |
Pull-up |
BC_1 |
D9 |
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123 |
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Enable |
BC_2a |
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124 |
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Input/Output |
BC_7 |
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D14 |
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C8 |
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125 |
Pull-up |
BC_1 |
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126 |
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Enable |
BC_2a |
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127 |
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Input/Output |
BC_7 |
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128 |
D15 |
Pull-up |
BC_1 |
A9 |
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129 |
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Enable |
BC_2a |
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130 |
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Input/Output |
BC_7 |
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B8 |
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131 |
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DE |
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Pull-up |
BC_1 |
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132 |
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Enable |
BC_2a |
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133 |
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Input/Output |
BC_7 |
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134 |
TXD |
Pull-up |
BC_1 |
D4 |
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135 |
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Enable |
BC_2a |
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136 |
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Input/Output |
BC_7 |
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RXD |
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B4 |
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137 |
Pull-up |
BC_1 |
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138 |
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Enable |
BC_2a |
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139 |
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Input/Output |
BC_7 |
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140 |
MOSI |
Pull-up |
BC_1 |
C5 |
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141 |
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Enable |
BC_2a |
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142 |
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Input/Output |
BC_7 |
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MISO |
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C4 |
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143 |
Pull-up |
BC_1 |
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144 |
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Enable |
BC_2a |
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145 |
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Input/Output |
BC_7 |
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146 |
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SS |
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Pull-up |
BC_1 |
B3 |
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147 |
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Enable |
BC_2a |
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148 |
SCK |
Input/Output |
BC_7 |
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149 |
Pull-up |
BC_1 |
A3 |
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150 |
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Enable |
BC_2a |
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151 |
SRXD |
Input/Output |
BC_7 |
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152 |
Pull-up |
BC_1 |
A2 |
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(GPIOC1) |
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153 |
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Enable |
BC_2a |
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154 |
STXD |
Input/Output |
BC_7 |
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155 |
Pull-up |
BC_1 |
B2 |
|
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(GPIOC0) |
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|
156 |
|
|
|
|
|
Enable |
BC_2a |
|
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|
|
|
|
|
|
JTAG Port, Rev. 4 |
|
|
||
Freescale Semiconductor |
|
|
|
|
|
|
|
14-15 |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |