Introduction

14.1 Introduction

This chapter describes the 56800E core-based family of chips, providing board and chip-level debugging and high-density circuit board testing specific to Joint Test Action Group (JTAG).

The 56852 provides board and chip-level testing capability through two on-chip modules, both accessed through the JTAG port/EOnCE module interface:

•Enhanced On-chip Emulation (EOnCE) module

•Test Access Port (TAP) and 16-state controller, also known as the JTAG port

Presence of the JTAG port/EOnCE module interface permits insertion of the device into a target system while retaining debug control. This capability is especially important for devices without an external bus, because it eliminates the need for an expensive cable to bring out the chip footprint required by a traditional emulator system.

The Enhanced OnCE (EOnCE) module is used in Digital Signal Controller (DSC) chips to debug application software employed with the chip. The port is a separate, on-chip block, allowing non-intrusive interaction with accessibility through the pins of the JTAG interface. The EOnCE module makes it possible to examine registers, memory, or on-chip peripherals’ contents in a special debug environment. This avoids sacrificing any user-accessible, on-chip resources to perform debugging procedures. Please refer to the 56F800E Core-Based Reference Manual (DSP56800ERM) for details about implementation of the 56852 EOnCE module.

The JTAG port is a dedicated user-accessible TAP compatible with the IEEE 1149.1a-1993 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards have led to the development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the JTAG. 56852 supports circuit board test strategies based on this standard.

Six dedicated pins interface to the TAP containing a 16-state controller. The TAP uses a boundary scan technique to test the interconnections between integrated circuits after they are assembled onto a Printed Circuit Board (PCB). Boundary scans allow observation and control signal levels at each component pin through a Shift Register placed next to each pin. This is important for testing continuity and determining if pins are stuck at a one or zero level.

Features

14.2 Features

Features of the Test Access Port (TAP) port include:

•Perform boundary scan operations to test circuit board electrical continuity

•Bypass the TAP for a given circuit board test by replacing the Boundary Scan Register (BSR) with a single-bit register

•Sample system pins during operation and transparently shift-out the results in the BSR

•Preload output pins prior to invoking the EXTEST instruction

•Disable the output drive to pins during circuit board testing

•Provide a means of accessing the EOnCE module controller and circuits to control a target system

•Query the IDCODE from any TAP in the system

•Force test data onto the peripheral outputs while replacing its BSR with a single bit register

•Enable/disable pull-up devices on peripheral boundary scan pins

14.3 Master Test Access Port (TAP)

The Master TAP consists of:

•Synchronous finite 16-bit state machine

•Eight-bit Instruction Register (IR)

•Chip Identification Register (CID)

•Bypass Register (BYPASS)

•Boundary Scan Register (BSR).

Please see Table 14-1 for additional information.

Master Test Access Port (TAP)

14.3.1 Signal Description

As described in IEEE 1149.1a, the JTAG port requires a minimum of four pins to support TDI, TDO, TCK, and TMS signals. The 56852 also uses the optional TRST input signal and the DE output signal used by the EOnCE module interface. Pin functions are described in Table 14-1.

TAP Block Diagram

14.4 TAP Block Diagram

Figure 14-1. Test Access Port (TAP) Block Diagram

14.5 JTAG Port Architecture

The TAP Controller is a simple state machine used to sequence the JTAG port through its varied operations:

•Serially shift in or out a JTAG port command

•Update and decode the JTAG port Instruction Register (JTAGIR)

•Serially input or output a data value

•Update a JTAG port or EOnCE module register

Note: The JTAG port supervises the shifting of data into and out of the EOnCE module through TDI and TDO pins respectively. In this case, the shifting is guided by the same controller used when shifting JTAG information.

The JTAG block diagram is illustrated in Figure 14-1. The JTAG port has four read/write registers:

1.Instruction Register (JTAGIR)

2.Chip Identification Register (CID)

3.Bypass Register (JTAGBR)

4.Boundary Scan Register (BSR)

Access to the EOnCE registers is described in the 56800E Reference Manual (DSP56800ERM).

JTAG Port Architecture

14.5.1 JTAG Instruction Register (JTAGIR) and Decoder

The TAP Controller contains an 8-bit instruction register. The instruction is presented to an instruction decoder during the update-instruction register state. Please see Section 14.8 for a description of the TAP Controller operating states. The instruction decoder interprets and executes the instructions according to the conditions defined by the TAP Controller state machine.

The 56852 includes the three mandatory public instructions:

1.BYPASS

2.SAMPLE/PRELOAD

3.EXTEST

The 56852 includes four public instructions:

1.CLAMP

2.HIGH-Z

3.IDCODE

4.TLM_SELECT

The eight bits B[7:0] of the IR, decode the nine instructions, illustrated in Figure 14-2 and its data provided in Table 14-2. All other encodings are reserved.

Figure 14-2. JTAGIR Register

CAUTION

Reserved JTAG instruction encodings should not be used. Hazardous operation of the chip could occur if these instructions are used.

JTAG Port Architecture

Table 14-2. Master TAP Instructions Opcode

14.5.1.1 External Test Instruction (EXTEST)

The External Test (EXTEST) instruction enables the BSR between TDI and TDO, including cells for all digital device signals and associated control signals. The EXTAL, RESET pins, and any codec pins associated with analog signals, are not included in the BSR path.

In EXTEST, the BSR is capable of scanning user-defined values onto output pins, capturing values presented to input signals and controlling the direction and value of bidirectional pins. EXTEST instruction asserts internal system reset for the controller system logic during its run in order to force a predictable internal state while performing external boundary scan operations.

14.5.1.2 Bypass Instruction (BYPASS)

The BYPASS instruction enables the single-bit bypass register between TDI and TDO, illustrated in Figure 14-3. This creates a Shift Register path from TDI to the bypass register and finally to TDO, circumventing the BSR. This instruction is used to enhance test efficiency by shortening the overall path between TDI and TDO when no test operation of a component is required. In this instruction, the controller system logic is independent of the TAP. When this instruction is selected, the test logic has no effect on the operation of the on-chip system logic, required in IEEE 1149.1-1993a.

TDI

D Q To TDO MUX

SHIFT_DR

CLOCK_DR CK

Figure 14-3. Bypass Register

JTAG Port Architecture

14.5.2 Sample and Preload Instructions (SAMPLE/PRELOAD)

The SAMPLE/PRELOAD instruction enables the BSR between TDI and TDO. When this instruction is selected, the test logic operation has no effect on the operation of the on-chip system logic. Nor does it have an effect on the flow of a signal between the system pin and the on-chip system logic, specified by IEEE 1149.1-1993a. This instruction provides two separate functions.

1.First, it provides a means to obtain a snapshot of system data and control signals (SAMPLE). The snapshot occurs on the rising edge of TCK in the Capture-DR controller state. The data can be observed by shifting it transparently through the BSR.

In a normal system configuration, many signals require external pull-ups assuring proper system operation. Consequently, the same is true for the SAMPLE/PRELOAD functionality. Data latched into the BSR during the Capture-DR controller state may not match the drive state of the package signal if the system requiring pull-ups are not present within the test environment.

2.The second function of the SAMPLE/PRELOAD instruction is to initialize the BSR output cells (PRELOAD) prior to selection of the CLAMP or EXTEST instruction. This initialization ensures known data appears on the outputs when executing EXTEST. The data held in the Shift Register stage is transferred to the output latch on the falling edge of TCK in the update Data Register (DR) controller state. Data is not presented to the pins until the CLAMP or EXTEST instruction is executed.

Note: Since there is no internal synchronization between the JTAG clock (TCK) and the system Clock (CLK), some form of external synchronization to achieve meaningful results when sampling system values using the SAMPLE/PRELOAD instruction must be provided.

14.5.2.1 Identification Code Instruction (IDCODE)

The IDCODE instruction enables the IDREGISTER between TDI and TDO. It is provided as a public instruction to allow the manufacturer part number and version of a component to be determined through the TAP.

14.5.2.2 TAP Linking Module Select Instruction (TLM_SEL)

TLM_SEL instruction is a user-defined JTAG instruction. It is used to disable the Master TAP and enable the TAP Linking Module (TLM). The TLM provides a means of connecting one or more TAPs in a multi-TAP design, responding to the IC’s test pins in IEEE 1149.1 scan operations. TLM serves as a community data register used to set the TAP linking configuration

JTAG Port Architecture

desired. The TLM Register is a 4-bit register, illustrated in Table 14-3, and enabled between TDI and TDO during a shift Data Register (DR) operation. It is updated on the Update DR operation.

Table 14-3. TLM Register

14.5.2.3 High-Z Instruction (HIGHZ)

The HIGHZ instruction enables the single-bit bypass register between TDI and TDO. It is provided as a public instruction in order to prevent having to drive the output signals back during circuit board testing. When the HIGHZ instruction is invoked, all output drivers are placed in an inactive-drive state. HIGHZ asserts internal system reset for the controller system logic for the duration of HIGHZ in order to force a predictable internal state while performing external boundary scan operations.

14.5.3 JTAG Chip Identification (CID) Register

The Chip Identification (CID) register is a 32-bit register providing a unique JTAG ID for the 56852. It is offered as a public instruction to allow the manufacturer, part number, and version of a component to be determined through the TAP. Figure 14-4 illustrates the CID register configuration.

Figure 14-4. JTAG Chip Identification (CID) Register

The device identification number for the initial release of the 56852 is $01F5401D.