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Поволжский государственный технологический университет

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ЦОС_Заочники2013 / Курсовая МПиЦОС 2011 / Справочная информация / Моторола / DSP568xx / DSP56852UM.pdf

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Table 13-5. GPIO E Memory Map (GPIOE_BASE = $1FFE70)

Address Offset	Register Acronym	Register Name	Access Type	Chapter Location

Base + $16	GPIO_E_PER	Peripheral Enable Register	Read/Write	Section 13.8.3

Base + $17	GPIO_E_DDR	Data Direction Register	Read/Write	Section 13.8.6

Base + $18	GPIO_E_DR	Data Register	Read/Write	Section 13.8.9

Base + $19	GPIO_E_PUR	Pull-Up Enable Register	Read/Write	Section 13.8.12

Add.	Register Name		15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Offset	Register Name		15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Offset
$16	PER	R	1	1	1	1	1	1	1	1	1	1	1	1	1	1	PE
$16	PER	W															PE
		W
$17	DDR	R	0	0	0	0	0	0	0	0	0	0	0	0	0	0	DD
$17	DDR	W
		W
$18	DR	R	0	0	0	0	0	0	0	0	0	0	0	0	0	0	DATA
$18	DR	W
		W
$19	PUR	R	1	1	1	1	1	1	1	1	1	1	1	1	1	1	PUE
$19	PUR	W
		W
				Read as 0
		R	0	Read as 0
		W		Reserved

Figure 13-4. GPIO E Register Map Summary

13.8 Register Descriptions

Base Addresses:

•GPIOA_BASE = $1FFE60

•GPIOC_BASE = $1FFE68

•GPIOE_BASE = $1FFE70

13.8.1 Port A Peripheral Enable Register (GPIOA_PER)

Base + $0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Read	1	1	1	1	1	1	1	1	1	1	1	1	1		PE
Write															PE
Write
Reset	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

Figure 13-5. Port A Peripheral Enable Register (GPIOA_PER)

See Programmer’s Sheet on Appendix page B-76

	General Purpose Input/Output (GPIO), Rev. 4
Freescale Semiconductor	13-7

-packaged product lines and part numbers indicated here currently are not	2010: MC13892
Commission, BGA	prior to September
order from the United States International Trade Freescale for import or sale in the United States
of an from
Because	available

13.8.1.1 Reserved—Bits 15–3

These bits are reserved or not implemented. They are read as 1 and cannot be modified by writing.

13.8.1.2 Peripheral Enable (PE)—Bits 2–0

These bits control whether a given pin is in either Normal or GPIO mode.

•0 = GPIO mode; pin operation is controlled by GPIO registers

•1 = Normal mode; pin operation is controlled by the EMI module

13.8.2 Port C Peripheral Enable Register (GPIOC_PER)

Base + $8	15	14	13	12	11	10	9	8	7	6	5	4	3		2	1	0
Read	1	1	1	1	1	1	1	1	1	1				PE
Write														PE
Write
Reset	1	1	1	1	1	1	1	1	1	1	1	1	1		1	1	1

Figure 13-6. Port C Peripheral Enable Register (GPIOC_PER)

See Programmer’s Sheet on Appendix page B-77

13.8.2.1 Reserved—Bits 15–6

These bits are reserved or not implemented. They are read as 1 and cannot be modified by writing.

13.8.2.2 Peripheral Enable (PE)—Bits 5–0

These bits control whether a given pin is in either Normal or GPIO mode.

•0 = GPIO mode; pin operation is controlled by GPIO registers

•1 = Normal mode; pin operation is controlled by the SPI or ISSI modules

13.8.3 Port E Peripheral Enable Register (GPIOE_PER)

Base + $16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1		0
Read	1	1	1	1	1	1	1	1	1	1	1	1	1	1		PE
Write																PE
Write
Reset	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1		1

Figure 13-7. Port E Peripheral Enable Register (GPIOE_PER)

See Programmer’s Sheet on Appendix page B-78

	56852 Digital Signal Controller User Manual, Rev. 4
13-8	Freescale Semiconductor

-packaged product lines and part numbers indicated here currently are not	2010: MC13892
Commission, BGA	prior to September
order from the United States International Trade Freescale for import or sale in the United States
of an from
Because	available

13.8.3.1 Reserved—Bits 15–2

These bits are reserved or not implemented. They are read as 1 and cannot be modified by writing.

13.8.3.2 Peripheral Enable (PE)—Bits 1–0

These bits control whether a given pin is in either Normal or GPIO mode.

•0 = GPIO mode; pin operation is controlled by GPIO registers

•1 = Normal mode; pin operation is controlled by the SCI module

13.8.4 Port A Data Direction Register (GPIOA_DDR)

Base + $1	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Read	0	0	0	0	0	0	0	0	0	0	0	0	0		DD
Write															DD
Write
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Figure 13-8. Port A Data Direction Register (GPIOA_DDR)

See Programmer’s Sheet on Appendix page B-79

13.8.4.1 Reserved—Bits 15–3

These bits are reserved or not implemented. They are read as 0 and cannot be modified by writing.

13.8.4.2 Data Direction (DDR)—Bits 2–0

These bits control the pins direction when in GPIO mode. In the Normal mode, these bits have no effect on the output enables or pull-up enables.

•0 = Pin is an input; pull-ups are dependent on value of PUE registers (default)

•1 = Pin is an output; pull-ups are disabled

13.8.5 Port C Data Direction Register (GPIOC_DDR)

Base + $9	15	14	13	12	11	10	9	8	7	6	5	4	3		2	1	0
Read	0	0	0	0	0	0	0	0	0	0				DD
Write														DD
Write
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0		0	0	0

Figure 13-9. Port C Data Direction Register (GPIOC_DDR)

See Programmer’s Sheet on Appendix page B-80

	General Purpose Input/Output (GPIO), Rev. 4
Freescale Semiconductor	13-9

-packaged product lines and part numbers indicated here currently are not	2010: MC13892
Commission, BGA	prior to September
order from the United States International Trade Freescale for import or sale in the United States
of an from
Because	available

13.8.5.1 Reserved—Bits 15–6

These bits are reserved or not implemented. They are read as 0 and cannot be modified by writing.

13.8.5.2 Data Direction (DDR)—Bits 5–0

These bits control the pins direction when in the GPIO mode. In the Normal mode, these bits have no effect on the output enables or pull-up enables.

•0 = Pin is an input; pull-ups are dependent on value of PUE registers (default)

•1 = Pin is an output; pull-ups are disabled

13.8.6 Port E Data Direction Register (GPIOE_DDR)

Base + $17	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1		0
Read	0	0	0	0	0	0	0	0	0	0	0	0	0	0		DD
Write																DD
Write
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0		0

Figure 13-10. Port E Data Direction Register (GPIOE_DDR)

See Programmer’s Sheet on Appendix page B-79

13.8.6.1 Reserved—Bits 15–2

These bits are reserved or not implemented. They are read as 0 and cannot be modified by writing.

13.8.6.2 Data Direction (DDR)—Bits 1–0

These bits control the pins direction when in the GPIO mode. In the Normal mode, these bits have no effect on the output enables or pull-up enables.

•0 = Pin is an input; pull-ups are dependent on value of PUE registers (default)

•1 = Pin is an output; pull-ups are disabled

13.8.7 Port A Data Register (GPIOA_DR)

Base + $2	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Read	0	0	0	0	0	0	0	0	0	0	0	0	0		DATA
Write															DATA
Write
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Figure 13-11. Port A Data Register (GPIOA_DR)

See Programmer’s Sheet on Appendix page B-82

	56852 Digital Signal Controller User Manual, Rev. 4
13-10	Freescale Semiconductor

-packaged product lines and part numbers indicated here currently are not	2010: MC13892
Commission, BGA	prior to September
order from the United States International Trade Freescale for import or sale in the United States
of an from
Because	available

13.8.7.1 Reserved—Bits 15–3

These bits are reserved or not implemented. They are read as 0 and cannot be modified by writing.

13.8.7.2 Data (DATA)—Bits 2–0

These bits control the output data when in the GPIO mode.

13.8.8 Port C Data Register (GPIOC_DR)

Base + $A	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Read	0	0	0	0	0	0	0	0	0	0			DATA
Write													DATA
Write
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Figure 13-12. Port C Data Register (GPIOC_DR)

See Programmer’s Sheet on Appendix page B-83

13.8.8.1 Reserved—Bits 15–6

These bits are reserved or not implemented. They are read as 0 and cannot be modified by writing.

13.8.8.2 Data (DATA)—Bits 5–0

These bits control the output data when in the GPIO mode.

13.8.9 Port E Data Register (GPIOE_DR)

Base + $18	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Read	0	0	0	0	0	0	0	0	0	0	0	0	0	0	DATA
Write															DATA
Write
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Figure 13-13. Port E Data Register (GPIOE_DR)

See Programmer’s Sheet on Appendix page B-84

13.8.9.1 Reserved—Bits 15–2

These bits are reserved or not implemented. They are read as 0 and cannot be modified by writing.

13.8.9.2 Data (DATA)—Bits 1–0

These bits control the output data when in the GPIO mode.

	General Purpose Input/Output (GPIO), Rev. 4
Freescale Semiconductor	13-11

-packaged product lines and part numbers indicated here currently are not	2010: MC13892
Commission, BGA	prior to September
order from the United States International Trade Freescale for import or sale in the United States
of an from
Because	available

13.8.10 Port A Pull-Up Enable Register (GPIOA_PUE)

Base + $3	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Read	1	1	1	1	1	1	1	1	1	1	1	1	1		PE
Write															PE
Write
Reset	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

Figure 13-14. Port A Pull-Up Enable Register (GPIOA_PUE)

See Programmer’s Sheet on Appendix page B-85

13.8.10.1 Reserved—Bits 15–3

These bits are reserved or not implemented. They are read as 1 and cannot be modified by writing.

13.8.10.2 Pull-Up Enable (PULLUP)—Bits 2–0

These bits control whether pull-ups are enabled for inputs in either Normal or GPIO modes. Pull-ups are automatically disabled for outputs in both modes.

•0 = Pull-ups disabled for inputs

•1 = Pull-ups enabled for inputs (default)

13.8.11 Port C Pull-Up Enable Register (GPIOC_PUE)

Base + $B	15	14	13	12	11	10	9	8	7	6	5	4	3		2	1	0
Read	1	1	1	1	1	1	1	1	1	1				PE
Write														PE
Write
Reset	1	1	1	1	1	1	1	1	1	1	1	1	1		1	1	1

Figure 13-15. Port C Pull-Up Enable Register (GPIOC_PUE)

See Programmer’s Sheet on Appendix page B-86

13.8.11.1 Reserved—Bits 15–6

These bits are reserved or not implemented. They are read as 1 and cannot be modified by writing.

13.8.11.2 Pull-Up Enable (PULLUP)—Bits 5–0

These bits control whether pull-ups are enabled for inputs in either Normal or GPIO modes. Pull-ups are automatically disabled for outputs in both modes.

•0 = Pull-ups disabled for inputs

•1 = Pull-ups enabled for inputs (default)

	56852 Digital Signal Controller User Manual, Rev. 4
13-12	Freescale Semiconductor

-packaged product lines and part numbers indicated here currently are not	2010: MC13892
Commission, BGA	prior to September
order from the United States International Trade Freescale for import or sale in the United States
of an from
Because	available

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