GPIO Block Diagram

13.1 Introduction

The 56852 General Purpose Input/Output (GPIO) is designed to share package pins with other peripheral modules on the chip. If a peripheral normally controlling a given pin is not required, then the pin can be programmed to be a GPIO with programmable pull-up.

13.2 Features

The GPIO module design includes:

•Individual control for each pin to be in either Normal or GPIO mode

•Individual direction control for each pin in GPIO mode

•Individual pull-up enable control for each pin in either Normal or GPIO mode

13.3 GPIO Block Diagram

General Purpose Input/Output (GPIO), Rev. 4

Functional Description

Table 13-1. Mapping of External Signals to GPIO Ports

13.4 Functional Description

Each GPIO pin can be configured as either an input, with or without pull-up, or an output. Pull-ups are configured by writing to the Pull-Up Registers and are automatically disabled when the pin is being used as an output in either the Normal or GPIO modes of operation.

13.5 Modes of Operation

The GPIO module design contains two major modes of operation:

13.5.1 Normal Mode

This can also be thought of as Peripheral Controlled mode. The peripheral module controls the output enable and any output data to the I/O pad and any input data from the pad is passed to the peripheral. Pull-up enables are controlled by a GPIO register.

13.5.2 GPIO Mode

In this mode, the GPIO module controls the output enable to the pad and supplies any data to be output. Also, any input data can be read from a GPIO memory mapped register. Pull-up enables are controlled by a GPIO register.

Module Memory Maps

In the GPIO mode, the Data Direction Register (DDR) supplies the output enable to the I/O pad to control its direction. The DR supplies the output data if DDR is asserted. The value of the data on the I/O pad can be read by reading Data Register (DR) when DDR is zero. When in GPIO mode the output data from the GPIO to the peripheral module will be driven high and the output data and enable from the peripheral are ignored. The pull-up resistor can be enabled by writing to the PUE Register. The pull-up resistor will be disabled as long as the DDR is set to the Output mode.

13.6 GPIO Configurations

Each GPIO port is controlled by the registers listed in Section 13-2. Each register bit corresponds to a GPIO pin. Figure 13-1 illustrates the logic associated with one GPIO bit.

Table 13-2. GPIO Registers Functions

13.7 Module Memory Maps

There are three GPIO mapped modules listed in the following in tables, Section 13-3 through Section 13-5. The GPIO peripherals are summarized in Figure 13-2 through Figure 13-4.

Table 13-3. GPIO A Memory Map (GPIOA_BASE = $1FFE60)

Module Memory Maps

Figure 13-2. GPIO A Register Map Summary

Table 13-4. GPIO C Memory Map (GPIOC_BASE = $1FFE68)

Figure 13-3. GPIO C Register Map Summary