56852 Peripheral Blocks

1.5 56852 Memory

The 56852 Memory module features:

•Harvard architecture permits as many as three simultaneous accesses to program and data memory

•On-chip memory includes:

—6K × 16-bit Program SRAM

—4K × 16-bit Data SRAM

—1K × 16-bit Boot ROM

•Up to 21-External Memory Address lines, 16-data lines and up to 4-programmable chip select signals

1.656852 Peripheral Blocks

The peripheral blocks on the 56852 provide:

•Four general purpose, 16-bit timers with two external pins*

•One Serial Communication Interface (SCI)*

•One Serial Port Interface (SPI)*

•Interrupt Controller

•Watchdog Timer (COP)

•JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging

•Up to 11-GPIO

* Each peripheral I/O can be used alternately as a general purpose I/O if they are not needed

1.6.1 Energy Information

•Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs

•Wait and Stop modes available

1.6.2 COP/Watchdog Timer Module

The Computer Operating Properly (COP) module provides the Watchdog timer functions. This function monitors processor activity and provides an automatic reset signal if a failure occurs.

•160-bit counter, providing (65536)10 different time-out periods

•COP timebase is the OSC clock divided by 128

•At 4MHz, minimum time-out period is 32µs, maximum is 2.1sec, with a resolution of 32µs

56852 Peripheral Blocks

1.6.3 Peripheral Interrupts/Interrupt Controller Module

The peripherals on the 56852 use the interrupt channels found on the 56800E core. Each peripheral has its own interrupt vector (often more than one interrupt vector for each peripheral), and can selectively be enabled or disabled via the IPR found on the core. The Interrupt Controller (ITCN) module design includes these distinctive features:

•Programmable priority levels for each IRQ

•Two programmable Fast Interrupts

•Notification to the SIM module to restart clocks out of Wait and Stop modes.

1.6.4 Serial Communications Interface Module (SCI)

The SCI module allows asynchronous serial communications with peripheral devices and other Microcontroller Units (MCUs). SCI features include:

•Full-duplex or single wire operation

•Standard mark/space Non-Return-to-Zero (NRZ) format

•13-bit baud rate selection

•Programmable 8-bit or 9-bit data format

•Separately enabled transmitter and receiver

•Separate receiver and transmitter CPU interrupt requests

•Programmable polarity for transmitter and receiver

•Two receiver wake up methods

•Interrupt-driven operation with seven flags

•Receiver framing error detection

•Hardware parity checking

•1/16 bit-time noise detection

1.6.5 Serial Peripheral Interface Module (SPI)

The Serial Peripheral Interface (SPI) is an independent serial communications subsystem allowing full-duplex, synchronous, serial communication between the controller and peripheral devices, including other controllers. Software can poll SPI status flags or SPI operation can be interrupt driven. This block contains four 16-bit memory mapped registers for control parameters, status, and data transfer.

The 56852 has one, 4-pin SPI alternately used as GPIO when the SPI is not required. The SPI features include:

56852 Peripheral Blocks

•Full-duplex operation

•Master and Slave modes

•Double-buffered operation with separate transmit and receive registers

•Programmable length transmissions (2 to 16 bits)

•Programmable transmit and receive shift order (MSB first or last bit transmitted)

•Eight Master mode frequencies (maximum = IPBus frequency 2)

•Maximum Slave mode frequency = IPBus frequency

•Clock ground for reduced Radio Frequency (RF) interference

•Serial clock with programmable polarity and phase

•Two separately enabled interrupts

—SPRF (SPI Receiver Full)

—SPTE (SPI Transmitter Empty)

•Mode fault error flag interrupt capability

•Wired OR mode functionality to enabling connection to multiple SPIs

1.6.6 Improved Synchronous Serial Interface Module (ISSI)

The ISSI is a full-duplex serial port designed to allow Digital Signal Controllers (DSCs) to communicate with a variety of serial devices, including industry-standard codecs, other controllers, microprocessors, and peripherals, including those implementing the Serial Peripheral Interface (SPI). It is typically used to transfer samples in a periodic manner. The ISSI consists of independent transmitter and receiver sections with independent clock generation and frame synchronization. Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal, external clocks and frame syncs. The Improved SSI (ISSI) features include:

•Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs

•Normal mode operation using frame sync

•Network mode operation allowing multiple devices to share the port with as many as 32-time slots

•Gated Clock mode operation requiring no frame sync

•Programmable internal clock divider

•Programmable word length (8, 10, 12, or 16 bits)

56852 Peripheral Blocks

•Program options for frame sync and clock generation

•ISSI power down feature

•Completely separate clock and frame sync selections for the receive and transmit sections

1.6.7 Quad Timer Module (TMR)

The Quad Timer (TMR) module has two external signals only available when the EMI A17/A18 are not in use. Otherwise, the two external signals of the module are capable of being used as either inputs or outputs. The two-pin Quad Timer provides the following features:

•Four 16-bit counters/timers

•Count up/down

•Counters can be cascaded

•Count modulo can be programmed

•Maximum count rate equals peripheral IPBus clock for external clocks

•Maximum count rate equals peripheral IPBus clock for internal clocks

•Count once or repeatedly

•Counters can be preloaded

•Counters can share available input pins

•Separate prescaler for each counter

•Each counter has capture and compare capability

1.6.8 General Purpose Input/Output Port (GPIO)

There are no GPIO interrupts on the 56852.

•Up to 11 shared GPIO, multiplexed with other peripherals

•Each bit can be individually configured as an input or output

•Selectable enable for pull-up resistors

1.6.9 Resets

The 56852 chip reset circuitry features:

•Integrated POR release occurs when the core VDD exceeds 1.8V.

Chapter 2

Pin Descriptions

Pin Descriptions, Rev. 4

Freescale Semiconductor

2-1