Module Memory Map

the counter output yields a Pulse Width Modulated (PWM) signal whose frequency and pulse width is determined by the values programmed into the TMR_CMP1 and TMR_CMP2 registers, and the input clock frequency. This method of PWM generation has the advantage of allowing almost any desired PWM frequency and/or constant on or off periods. This mode of operation is often used to drive PWM amplifiers used to power motors and inverters.

12.7.13 Compare Registers Use

The dual Compare registers (TMR_CMP1 and TMR_CMP2) provide a bidirectional modulo count capability. The CMP1 Register is used when the counter is counting up, and the CMP2 Register is used when the counter is counting down. The only exception is when the counter is operating with alternating compare registers. The CMP1 Register should be set to the desired maximum count value or $FFFF to indicate the maximum unsigned value prior to roll-over, and the CMP2 Register should be set to the maximum negative count value or $0000 indicating the maximum unsigned value prior to roll-under.

If the Output mode is set to 100, the OFLAG will toggle while using alternating Compare registers. In this Variable Frequency PWM mode, the CMP2 value defines the desired pulse width of the on-time, and the CMP1 Register defines the off-time. The Variable Frequency PWM mode is defined for positive counting only.

One must be careful when changing CMP1 and CMP2 while the counter is active. If the counter has already passed the new value, it will count to $FFFF or $0000, roll over/under, and then begin counting toward the new value. (The check is for Count = Cmpx, not Count> = Cmp1 or Count < = Cmp2).

12.7.14 Capture Register Use

The Capture Register stores a copy of the counter’s value when an input edge (positive, negative, or both) is detected. Once a capture event occurs, no further updating of the Capture Register will occur until the Input Edge Flag (IEF) is cleared by writing 0 to the IEF.

12.8 Module Memory Map

There are eight registers on the TMR peripheral described in Table 12-1.

Module Memory Map

Table 12-1. TMR Module Memory Map (TMR_BASE = $1FFE80)

Figure 12-3. TMR Register Map Summary

Register Descriptions (TMR_BASE = $1FFE80)

12.9 Register Descriptions (TMR_BASE = $1FFE80)

12.9.1 Timer Control Registers (CTL)

There are four Timer Control Registers in this occurrence. Their addresses are:

TMRA0_CTRL (Timer A, Channel 0 Control)—Address: TMRA_BASE + $6

TMRA1_CTRL (Timer A, Channel 1 Control)—Address: TMRA_BASE + $E

TMRA2_CTRL (Timer A, Channel 2 Control)—Address: TMRA_BASE + $16

TMRA3_CTRL (Timer A, Channel 3 Control)—Address: TMRA_BASE + $1E

Figure 12-4. TMR Control Register (CTL)

See Programmer’s Sheet on Appendix page B-65

12.9.1.1 Count Mode (CM)—Bits 15–13

These bits control the basic counting behavior of the counter.

•000 = No operation

•001 = Count rising edges of primary source1

•010 = Count rising and falling edges of primary source

•011 = Count rising edges of primary source while secondary input high active1

•100 = Quadrature count mode, uses primary and secondary sources

•101 = Count rising edges of primary source; secondary source specifies direction (1 = minus)1

•110 = Edge of secondary source triggers primary count until compare

•111 = Cascaded Counter mode (up/down)2

12.9.1.2 Primary Count Source (PCS)—Bits 12–9

These bits select the Primary Count Source.

•0000 = Counter 0 pin (TIO0)

•0001 = Counter 1 pin (TIO1)

•0010 = Counter 2 pin (TIO2)

1.Rising edges counted only when IPS = 0. Falling edges counted when IPS = 1.

2.Primary Count Source must be set to one of the counter outputs.

Register Descriptions (TMR_BASE = $1FFE80)

•0011 = Counter 3 pin (TIO3)

•0100 = Counter 0 OFLAG

•0101 = Counter 1 OFLAG

•0110 = Counter 2 OFLAG

•0111 = Counter 3 OFLAG

•1000 = Prescaler (IPBus clock divide by 1)

•1001 = Prescaler (IPBus clock divide by 2)

•1010 = Prescaler (IPBus clock divide by 4)

•1011 = Prescaler (IPBus clock divide by 8)

•1100 = Prescaler (IPBus clock divide by 16)

•1101 = Prescaler (IPBus clock divide by 32)

•1110 = Prescaler (IPBus clock divide by 64)

•1111 = Prescaler (IPBus clock divide by 128)

Note: A timer selecting its own output for input is not a legal choice. The result is no counting.

12.9.1.3 Secondary Count Source (SCS)—Bits 8–7

These bits provide additional information, such as direction, used for counting. They also define the source used by both the Capture mode bits and the Input Edge Flag in the Channel Status and Control register.

•00 = Counter 0 pin (TIO0)

•01 = Counter 1 pin (TIO1)

•10 = Counter 2 pin (TIO2)

•11 = Counter 3 pin (TIO3)

12.9.1.4 Count Once (ONCE)—Bit 6

This bit select continuous or one shot counting mode.

•0 = Count repeatedly

•1 = Count until compare and then stop. If counting up, successful compare occurs when counter reaches CMP1 value. If counting down, successful compare occurs when counter reaches CMP2 value. When the compare occurs the timer is stopped by changing the timer’s Count mode to Stop Mode (CM=0).

Register Descriptions (TMR_BASE = $1FFE80)

12.9.1.5 Count Length (LENGTH)—Bit 5

This bit determines whether the counter counts to the compare value and then reinitializes itself, or the counter continues counting past the compare value (binary roll-over).

•0 = Roll-over

•1 = Count till compare, then reinstalled. If counting up, successful compare occurs when

counter reaches CMP1 value. If counting down, successful compare occurs when counter reaches CMP2 value.1

12.9.1.6 Count Direction (DIR)—Bit 4

This bit selects either the normal count up direction, or the reverse down direction.

•0 = Count Up

•1 = Count Down

12.9.1.7 External Initialization (EXT INIT)—Bit 3

This bit enables another counter/timer within the same module to force the re-initialization of this counter/timer when the other counter has an active compare event.

•0 = External counter/timers can not force a re-initialization of this counter/timer.

•1 = External counter/timers may force a re-initialization of this counter/timer.

12.9.1.8 Output Mode (OM)—Bits 2–0

These bits determine the mode of operation for the OFLAG output signal.

•000 = Asserted while counter is active

•001 = Clear OFLAG output on successful compare

•010 = Set OFLAG output on successful compare

•011 = Toggle OFLAG output on successful compare

•100 = Toggle OFLAG output using alternating compare registers

•101 = Set on compare, cleared on secondary source input edge

•110 = Set on compare, cleared on counter rollover

•111 = Enable Gated Clock output while counter is active2

1.When the Output mode 0×4 is used, alternating values of CMP1 and CMP2 are used to generate successful compares. For example, when the Output mode is 0×4, the counter counts until CMP1 value is reached, reinitializes, then counts until CMP2 value is reached, reinitializes, then counts until CMP1 value is reached, and so on.

2.Primary Count Source must be set to one of the counter outputs

2.Primary Count Source must be set to one of the counter outputs.

Register Descriptions (TMR_BASE = $1FFE80)

Note: Unexpected results may occur if the Output mode field is set to use alternating Compare registers (mode 100) and the Count Once bit is set.

12.9.2 Timer Channel Status and Control Registers (SCR)

There are four Timer Status and Control Registers in this occurrence. Their addresses are:

Figure 12-5. TMR Status and Control Register (SCR)

See Programmer’s Sheet on Appendix page B-68

12.9.2.1 Timer Compare Flag (TCF)—Bit 15

This bit is set when a successful compare occurs. Clear the bit by writing 0 to it.

12.9.2.2 Timer Compare Flag Interrupt Enable (TCFIE)—Bit 14

When set, this bit enables interrupts when the TCF bit is set.

12.9.2.3 Timer Overflow Flag (TOF)—Bit 13

This bit is set when the counter rolls over its maximum value $FFFF or $0000, depending on count direction. Clear the bit by writing 0 to it.

12.9.2.4 Timer Overflow Flag Interrupt Enable (TOFIE)—Bit 12

When set, this bit enables interrupts when the TOF bit is set.

12.9.2.5 Input Edge Flag (IEF)—Bit 11

This bit is set when a positive input transition occurs while the counter is enabled. Clear the bit by writing 0 to it.

Note: Setting the input polarity select (IPS) bit enables the detection of negative input edge transitions detection. Also, the control register’s Secondary Count Source determines which external input pin is monitored by the detection circuitry.

Register Descriptions (TMR_BASE = $1FFE80)

12.9.2.6 Input Edge Flag Interrupt Enable (IEFIE)—Bit 10

When set, this bit enables interrupts when the IEF bit is set

12.9.2.7 Input Polarity Select (IPS)—Bit 9

When set, this bit inverts the polarity of both the primary and secondary inputs..

12.9.2.8 External Input Signal (INPUT)—Bit 8

This bit reflects the current state of the external input pin selected via the Secondary Count Source after application of the IPS bit. This is a read-only bit.

12.9.2.9 Input Capture Mode (Capture Mode)—Bits 7–6

These bits specify the operation of the Capture Register as well as the operation of the input edge flag.

•00 = Capture function is disabled.

•01 = Load Capture register on rising edge of input

•10 = Load Capture Register on falling edge of input

•11 = Load Capture Register on any edge of input

12.9.2.10 Master Mode (MSTR)—Bit 5

When set, this bit enables the Compare function’s output to be broadcasted to the other counter/timers in the module. This signal then can be used to reinitialize the other counters and/or force their OFLAG signal outputs.

12.9.2.11 Enable External OFLAG Force (EEOF)—Bit 4

When set, this bit enables the compare from another counter/timer within the same module to force the state of this counters’ OFLAG Output signal.

12.9.2.12 Forced OFLAG Value (VAL)—Bit 3

This bit determines the value of the OFLAG Output signal when a software triggered FORCE command occurs.

Register Descriptions (TMR_BASE = $1FFE80)

12.9.2.13 Force OFLAG Output (FORCE)—Bit 2

This write-only bit forces the current value of the VAL bit to be written to the OFLAG Output. Always read this bit as 0. The VAL and FORCE bits can be written simultaneously in a single write operation. Write to the FORCE bit only if the counter is disabled.

•0 = No action

•1 = Forces the current value of the VAL bit to be written to OFLAG Output

Note: Setting this bit while the counter is enabled may yield unpredictable results.

12.9.2.14 Output Polarity Select (OPS)—Bit 1

This bit determines the polarity of the OFLAG Output signal.

•0 = True polarity

•1 = Inverted polarity

12.9.2.15 Output Enable (OEN)—Bit 0

When set, this bit enables the OFLAG Output signal to be put on the external pin. Additionally, setting this bit connects a timer’s output pin to its input. The polarity of the signal will be determined by the OPS bit.

12.9.3 Timer Channel Compare Register 1 (CMP1)

These read/write registers store the value used for comparison with counter value. There are four Timer Channel Compare Registers in this occurrence. Their addresses are:

TMRA0_CMP1 (Timer A, Channel 0 Compare 1)—Address:TMRA_BASE + $0

TMRA1_CMP1 (Timer A, Channel 1 Compare 1)—Address: TMRA_BASE + $8

TMRA2_CMP1 (Timer A, Channel 2 Compare 1)—Address:TMRA_BASE + $10

TMRA3_CMP1 (Timer A, Channel 3 Compare 1)—Address: TMRA_BASE + $18

Figure 12-6. TMR Compare Register 1 (CMP1)

See Programmer’s Sheet on Appendix page B-70

Register Descriptions (TMR_BASE = $1FFE80)

12.9.4 Timer Channel Compare Register 2 (CMP2)

These read/write registers store the value used for comparison with counter value. There are four Timer Compare Registers in this occurrence. Their addresses are:

TMRA0_CMP2 (Timer A, Channel 0 Compare 2)—Address: TMRA_BASE + $1

TMRA1_CMP2 (Timer A, Channel 1 Compare 2)—Address: TMRA_BASE + $9

TMRA2_CMP2 (Timer A, Channel 2 Compare 2)—Address: TMRA_BASE + $11

TMRA3_CMP2 (Timer A, Channel 3 Compare 2)—Address: TMRA_BASE + $19

Figure 12-7. TMR Compare Register 2 (CMP2)

See Programmer’s Sheet on Appendix page B-71

12.9.5 Timer Channel Capture Register (CAP)

These read/write registers store the values captured from the counters. There are four Timer Channel Hold Registers in this occurrence. Their addresses are:

TMRA0_CAP (Timer A, Channel 0 Capture)—Address: TMRA_BASE + $2

TMRA1_CAP (Timer A, Channel 1 Capture)—Address: TMRA_BASE + $A

TMRA2_CAP (Timer A, Channel 2 Capture)—Address: TMRA_BASE + $12

TMRA3_CAP (Timer A, Channel 3 Capture)—Address: TMRA_BASE + $1A

Figure 12-8. TMR Capture Register (CAP)

See Programmer’s Sheet on Appendix page B-72

Register Descriptions (TMR_BASE = $1FFE80)

12.9.6 Timer Channel Load Register (LOAD)

These read/write registers store the value used to load the counter. There are four Timer Channel Load Registers in this occurrence. Their addresses are:

Figure 12-9. TMR Load Register (LOAD)

See Programmer’s Sheet on Appendix page B-73

12.9.7 Timer Channel Hold Register (HOLD)

These read/write registers store the channel’s value whenever any counter is read. There are four Timer Channel Hold Registers in this occurrence. Their addresses are:

TMRA0_HOLD (Timer A, Channel 0 Load)—Address: TMRA_BASE + $4

TMRA1_HOLD (Timer A, Channel 1 Load)—Address: TMRA_BASE + $C

TMRA2_HOLD (Timer A, Channel 2 Load)—Address: TMRA_BASE + $14

TMRA3_HOLD (Timer A, Channel 3 Load)—Address: TMRA_BASE + $1C

Figure 12-10. TMR Hold Register (HOLD)

See Programmer’s Sheet on Appendix page B-74