Features

12.1 Introduction

The Quad Timer (TMR) module contains four identical counter/timer groups. Each 16-bit counter/timer group contains a

•Prescaler

•Counter

•Load register

•Hold register

•Capture register

•Two Compare registers

•Two Status and Control registers

All except the prescaler are read/write registers.

Note: This document uses the terms Timer and Counter interchangeably because the counter/timers may perform either or both tasks.

The Load Register provides the initialization value to the counter when the counter’s terminal value has been reached. The Hold registers capture the counter’s value the instant any counter register is read. This feature supports the reading of cascaded counters. The Capture Register enables an external signal to take a snapshot of the counter’s current value. The TMR_CMP1 and TMR_CMP2 registers provide the values to which the counter is compared. If a match occurs, the OFLAG signal can be set, cleared, or toggled. At match time, an interrupt is generated if enabled. The Prescaler provides different IPBus Clock time bases useful for clocking the counter. The Counter provides the ability to count internal or external events. Input pins are shared within a Timer module.

12.2 Features

The Quad TMR module design includes these distinctive capabilities:

•Four, 16-bit counters/timers

•Count up/down

•Counters are cascadable

•Count modulo can be programmed

•Maximum count rate equals peripheral clock for external clocks

•Maximum count rate equals peripheral clock for internal clocks

•Count once or repeatedly

Operating Modes

•Counters can be preloaded

•Counters can share available input pins

•Separate prescaler for each counter

•Each counter has capture and compare capability

12.3 Operating Modes

The TMR module design operates in only the Functional mode. Various counting modes are detailed in Functional Description, Section 12.6.

12.4 Block Diagram

The block diagram of the Quad TMR module is illustrated in Figure 12-1.

Figure 12-1. TMR Module Block Diagram

12.5 Signal Description

The TMR module has four external signals TIO[3:0] with the capability to be used as either inputs or outputs.

12.6 Functional Description

The counter/timer has two basic modes of operation:

1.Count internal or external events

2.Count an internal clock source while an external input signal is asserted, thus timing the width of the external input signal

56852 Digital Signal Controller User Manual, Rev. 4

Counting Modes Definitions

The counter can count the rising, falling, or both edges of the selected input pin. The counter can decode and count quadrature encoded input signals. The counter can count up and down using dual inputs in a count with direction format. The counter’s terminal count value (modulo) is programmable. The value loaded into the counter after reaching its terminal count is programmable. The counter can count repeatedly, or it can stop after completing one count cycle. The counter can be programmed to count to a programmed value and then immediately reinitialize, or it can count through the compare value until the count rolls over to zero.

The external inputs to each counter/timer can be shared among each of the four counter/timers within the module. The external inputs can be used as:

•Count commands

•Timer commands

•Trigger current counter value to be captured

•Generate interrupt requests

The polarity of the external inputs can be selected. For this implementation of the Timer (TMR), there are four input pins. The primary output of each timer/counter is the output signal, OFLAG. The OFLAG output signal can be set, cleared, or toggled when the counter reaches the programmed value. The OFLAG output signal may be output to an external pin shared with an external input signal (TIOx).

The OFLAG output signal enables each counter to generate square waves (PWM) or pulse stream outputs. The polarity of the OFLAG output signal is selectable.

Any counter/timer can be assigned as a Master (MSTR). A master’s compare signal can be broadcasted to the other counter/timers within the module. The other counters can be configured to reinitialize their counters and/or force their OFLAG output signals to predetermined values when a Master’s Counter/Timer compare event occurs.

12.7 Counting Modes Definitions

The selected external count signals are sampled at the TMR’s base clock rate (60MHz) and then run through a transition detector. The maximum count rate is one-half of the base peripheral clock rate. Internal clock sources can be used to clock the counters at the peripheral clock rate.

If a counter is programmed to count to a specific value and then stop, the Count mode in the TMR_CTRL register is cleared when the count terminates.

12.7.1 Stop Mode

If the Count mode field is set to 000, the counter is inert. No counting will occur.

Counting Modes Definitions

12.7.2 Count Mode

If the Count mode field is set to 001, the counter will count the rising edges of the selected clock source. This mode is useful for generating periodic interrupts for timing purposes, or counting external events such as widgets on a conveyor belt passing a sensor. If the selected input is inverted by setting the Input Polarity Select (IPS) bit, the negative edge of the selected external input signal is counted.

12.7.3 Edge Count Mode

If the Count mode field is set to 010, the counter will count both edges of the selected external clock source. This mode is useful for counting the changes in the external environment such as a simple encoder wheel.

12.7.4 Gated Count Mode

If the Count mode field is set to 011, the counter will count while the selected secondary input signal is high. This mode is used to time the duration of external events. If the selected input is inverted by setting the Input Polarity Select (IPS) bit, the counter will count while the selected secondary input is low.

12.7.5 Quadrature Count Mode

When the Count mode field is set to 100, the counter will decode the primary and secondary external inputs as quadrature encoded signals. Quadrature signals are usually generated by rotary or linear sensors used to monitor movement of motor shafts or mechanical equipment. The quadrature signals are square waves, 90 degrees out-of-phase. The decoding of quadrature signal provides both count and direction information. A timing diagram illustrating the basic operation of a quadrature incremental position encoder is provided in Figure 12-2.

Figure 12-2. Quadrature Incremental Position Encoder

Counting Modes Definitions

12.7.6 Signed Count Mode

If the Count mode field is set to 101, the counter counts the primary clock source while the selected secondary source provides the selected count direction (up/down).

12.7.7 Triggered Count Mode

If the Count mode field is set to 110, the counter will begin counting the primary clock source after a positive transition (Negative Edge if IPS = 1) of the secondary input occurs. The counting will continue until a compare event occurs, or another positive input transition is detected. If a second input transition occurs before a terminal count was reached, counting will stop. Subsequent odd numbered edges of the secondary input will restart counting, while even numbered edges will stop counting. This will continue until a compare event occurs.

12.7.8 One-Shot Mode

This is a sub mode of triggered event Count mode if the count mode field is set to 110 while:

•Count Length (LENGTH) is set

•OFLAG Output mode is set to 101

•ONCE bit of the Control Register (CTRL) is set to 1

In the above setting, the counter works in a One-Shot mode. An external event causes the counter to count. When terminal count is reached, the OFLAG output is asserted. This delayed output assertion can be used to provide timing delays.

12.7.9 Cascade Count Mode

If the Count mode field is set to 111, the counter’s input is connected to the output of another selected counter. The counter will count up and down as compare events occur in the selected source counter. This Cascade or Daisy-Chained mode enables multiple counters to be cascaded in order to yield longer counter lengths. When operating in the Cascade mode, a special high speed signal path is used not using the OFLAG Output signal. If the Selected Source Counter is counting up, and it experiences a compare event, the counter will be incremented. If the selected source counter is counting down and it experiences a compare event, the counter will be decremented. Up to four counters may be cascaded to create a 64-bit wide synchronous counter. Whenever any counter is read within a Counter module, all of the counters’ values within the module are captured in their respective Hold Registers. This action supports the reading of a cascaded counter chain. First read any counter of a cascaded counter chain, then read the Hold Registers of the other counters in the chain. The Cascaded Counter mode is synchronous.

Counting Modes Definitions

Note: It is possible to connect counters together by using the other (non-cascade) Counter modes and selecting the outputs of other counters as a clock source. In this case, the counters are operating in a ripple mode, where higher order counters will transition a clock later than a purely synchronous design.

12.7.10 Pulse Output Mode

The Counter will output a pulse stream of pulses with the same frequency of the selected clock source (can not be IPBus clock divided by one) if the counter is setup for:

•Count mode (mode = 001)

•The OFLAG Output mode is set to 111 (Gated Clock Output)

•The Count Once bit is set

The number of output pulses is equal to the compare value minus the initial value. This mode is useful for driving step motor systems.

Note: Primary Count Source must be set to one of the counter outputs for gated clock output mode.

12.7.11 Fixed Frequency PWM Mode

The Counter output yields a Pulse Width Modulated (PWM) signal with a frequency equal to the count clock frequency divided by 65,536. It has a pulse width duty cycle equal to the compare value divided by 65,536 if the counter is setup for:

•Count mode (mode = 001)

•Count through roll-over (Count Length = 0)

•Continuous count (Count Once = 0)

•OFLAG Output mode is 110 (set on compare, cleared on counter rollover)

This mode of operation is often used to drive PWM amplifiers used to power motors and inverters.

12.7.12 Variable Frequency PWM Mode

If the counter is setup for:

•Count mode (Mode = 001)

•Count till compare (Count Length = 1)

•Continuous count (Count Once = 0)

•OFLAG Output mode is 100 (toggle OFLAG and alternate compare registers)