Features

11.1 Introduction

This chapter describes the Improved Synchronous Serial Interface (ISSI), by discussing the architecture, programming model, operating modes, and initialization of the ISSI. The ISSI is a full-duplex, serial port allowing Digital Signal Controller (DSCs) to communicate with a variety of serial devices, including industry-standard codecs, other DSCs, microprocessors, and peripherals implementing the Serial Peripheral Interface (SPI). It is typically used to transfer samples in a periodic manner. The ISSI consists of independent transmitter and receiver sections with independent clock generation and frame synchronization.

11.2 Features

ISSI features include:

•Independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs

•Normal mode operation using frame sync

•Network mode operation allowing multiple devices to share the port with as many as thirty-two time-slots

•Gated Clock mode operation requiring no frame sync

•Programmable internal clock divider

•Programmable word length (8, 10, 12, or 16 bits)

•Program options for frame sync and clock generation

•ISSI power down feature

Signal Descriptions

11.3.2External Signal Descriptions

11.3.2.1 ISSI Transmit Clock (STCK)

This pin can be configured as either an input or an output pin. This clock signal is used by the transmitter. It can be either continuous or gated. During Gated Clock mode, the STCK pin is active only during the transmission of data, otherwise it is inactive (low). In the Synchronous mode, this pin is used by both the transmit and receive sections.

11.3.2.2 ISSI Transmit Frame Sync (STFS)

This pin can be configured as either an input or an output pin. The frame sync is used by the transmitter to synchronize the transfer of data. The frame sync signal can be one bit or one word in length. The start of the frame sync can occur one bit before the transfer of data or right at the start of the data transfer.

In the Synchronous mode this pin is used by both the transmit and receive sections. Frame sync signals are not used in the Gated Clock mode.

11.3.2.3 ISSI Receive Clock (SRCK)

This pin can be configured as either an input or an output pin. This clock signal is used by the receiver. It can be either continuous or gated. During the Gated Clock mode, the STFS pin is active only during the reception of data, otherwise it is inactive, or low.

In the Synchronous mode, this pin is not used and can be configured as a GPIO pin.

Block Diagram

11.3.2.4 ISSI Receive Frame Sync (SRFS)

This pin can be configured as either an input or an output pin. The frame sync is used by the receiver to synchronize the transfer of data. The frame sync signal can be one bit or one word in length. The start of the frame sync can occur one bit before the transfer of data or right at the start of the data transfer.

In the Synchronous mode, this pin is not used and can be configured as a GPIO pin.

11.3.2.5 ISSI Transmit Data (STX)

This pin transmits data from the Serial Transmit Shift Register (STSR). The STXD pin is an output pin when data is being transmitted. It is inactive (High-Z) between data word transmissions.

11.3.2.6 ISSI Receive Data (SRX)

This pin is used to bring serial data into the Receive Data Shift Register (RXSR).

11.4 Block Diagram

The ISSI block diagram is detailed in Figure 11-1. The diagram consists of:

•Three control registers to set up the port

•One status/control register

•Separate transmit and receive circuits with FIFO registers

•Separate serial clock and frame sync generation for the transmit and receive sections

ISSI Configurations

Figure 11-1. ISSI Block Diagram

11.5 ISSI Configurations

Figure 11-21 and Figure 11-22 illustrate the main ISSI configurations. These pins support all transmit and receive functions with continuous or gated clock as shown. Table 11-5 describes the clock, frame sync, and data timing relationships in each of the modes available. Note gated clock implementations do not require the use of the frame sync pins. In this case, these pins can be used as GPIO pins, if desired.

56852 Digital Signal Controller User Manual, Rev. 4

ISSI Configurations

Note: The GPIO is a separate module, and alternatively controls the function and state of the I/O pins. Please see the GPIO module definition for alternate functions of the I/O pins defined here.

ISSI+GPIO

STXD

SRXD

STCK

STFS

SRCK

SRFS

ISSI Internal Continuous Clock (RXDIR=1,TXDIR=1,RFDIR=1,TFDIR=1,SYN=0)

ISSI+GPIO

STXD

SRXD

STCK

STFS

SRCK

SRFS

ISSI External Continuous Clock (RXDIR=0,TXDIR=0,RFDIR=0,TFDIR=0,SYN=0)

ISSI+GPIO

STXD

SRXD

STCK

STFS

SRCK

SRFS

ISSI Continuous Clock (RXDIR=1, TXDIR=0,RFDIR=1,TFDIR=0, SYN=0)

ISSI+GPIO

STXD

SRXD

STCK

STFS

SRCK

SRFS

ISSI Continuous Clock (RXDIR=0, TXDIR=1, RFDIR=0, TFDIR=1, SYN=0)

Figure 11-2. Asynchronous (SYN=0) ISSI Configurations—Continuous Clock

ISSI Configurations

ISSI+GPIO

STXD

SRXD

STCK

STFS

ISSI Internal Continuous Clock (RXDIR=0, TXDIR=1, RFDIR=X, TFDIR=1, SYN=1)

ISSI+GPIO

STXD

SRXD

STCK

STFS

ISSI External Continuous Clock (RXDIR=0, TXDIR=0, RFDIR=X, TFDIR=0,SYN=1)

ISSI+GPIO

STXD

SRXD

STCK

ISSI Internal Gated Clock (RXDIR=1, TXDIR=1, SYN=1)

ISSI+GPIO

STXD

SRXD

STCK

ISSI External Gated Clock (RXDIR=1, TXDIR=0, SYN=1)

Figure 11-3. Synchronous ISSI Configurations—Continuous and Gated Clock