- •Preface
- •About This Manual
- •Audience
- •Manual Organization
- •Suggested Reading
- •Manual Conventions
- •1.1 Introduction
- •1.2 56800E Core Description
- •1.3 56852 Architectural Overview
- •1.4 System Bus Controller
- •1.5 56852 Memory
- •1.6 56852 Peripheral Blocks
- •2.1 Introduction
- •2.2 Features
- •2.3 Signal and Package Information
- •3.1 Introduction
- •3.2 Program Boot ROM
- •3.3 Memory Map
- •4.1 Introduction
- •4.2 Features
- •4.3 SIM Block Diagram
- •4.4 Signal Description
- •4.5 Module Memory Map
- •4.6 Register Descriptions (SYS_BASE = $1FFF08)
- •4.7 Implementation
- •4.8 Generated Clocks
- •4.9 Generated Resets
- •4.10 Power Mode Controls
- •5.1 Introduction
- •5.2 Features
- •5.3 Functional Description
- •5.4 Block Diagram
- •5.5 Module Memory Map
- •5.6 Register Descriptions (EMI_BASE = $1FFE40)
- •5.7 Timing Specifications
- •5.8 Clocks
- •5.9 Interrupts
- •5.10 Resets
- •6.1 Introduction
- •6.2 OSC (Oscillator) Circuit Detail
- •6.3 Phase Locked Loop (PLL) Circuit Detail
- •6.4 CGM Functional Detail
- •6.5 Module Memory Map
- •6.6 Register Descriptions (CGM_BASE = $1FFF10)
- •6.7 OCCS Resets
- •6.8 OCCS Interrupts
- •7.1 Introduction
- •7.2 Features
- •7.3 Block Diagram
- •7.4 Method of Operation
- •7.5 Computer Operating Properly (COP) Module
- •7.6 Operating Modes
- •7.7 Block Diagram
- •7.8 Module Memory Map
- •7.9 Register Descriptions (COP_BASE = $1FFFD0)
- •7.10 Clocks
- •7.11 Resets
- •7.12 Interrupts
- •8.1 Introduction
- •8.2 Features
- •8.3 ITCN Module Signal Description
- •8.4 Block Diagram
- •8.5 Functional Description
- •8.6 Operating Modes
- •8.7 Wait and Stop Modes Operations
- •8.8 Module Memory Map
- •8.9 Register Descriptions (ITCN_BASE = $1FFF20)
- •8.10 Resets
- •8.11 Interrupts
- •9.1 Introduction
- •9.2 Features
- •9.3 Block Diagram
- •9.4 Signal Descriptions
- •9.5 Functional Description
- •9.6 Low Power Modes
- •9.7 Module Memory Map
- •9.8 Register Descriptions (SCI_BASE = $1FFFE0)
- •9.9 Clocks
- •9.10 Resets
- •9.11 Interrupts
- •10.1 Introduction
- •10.2 Features
- •10.3 SPI Block Diagram
- •10.4 Signal Descriptions
- •10.5 External I/O Signals
- •10.6 Operating Modes
- •10.7 Transmission Formats
- •10.8 Transmission Data
- •10.9 Error Conditions
- •10.10 Module Memory Map
- •10.11 Registers Descriptions (SPI_BASE = $1FFFE8)
- •10.12 Resets
- •10.13 Interrupts
- •11.1 Introduction
- •11.2 Features
- •11.3 Signal Descriptions
- •11.4 Block Diagram
- •11.5 ISSI Configurations
- •11.6 Module Memory Map
- •11.7 Register Descriptions (ISSI_BASE = $1FFE20)
- •11.8 ISSI Operating Modes
- •11.9 Clocks
- •11.10 Clock Operation Description
- •11.11 Resets
- •11.12 Interrupts
- •11.13 User Notes
- •12.1 Introduction
- •12.2 Features
- •12.3 Operating Modes
- •12.4 Block Diagram
- •12.5 Signal Description
- •12.6 Functional Description
- •12.7 Counting Modes Definitions
- •12.8 Module Memory Map
- •12.9 Register Descriptions (TMR_BASE = $1FFE80)
- •12.10 Resets
- •12.11 Interrupts
- •13.1 Introduction
- •13.2 Features
- •13.3 GPIO Block Diagram
- •13.4 Functional Description
- •13.5 Modes of Operation
- •13.6 GPIO Configurations
- •13.7 Module Memory Maps
- •13.8 Register Descriptions
- •13.9 Data Register Access
- •13.10 Resets
- •13.11 Interrupts
- •14.1 Introduction
- •14.2 Features
- •14.3 Master Test Access Port (TAP)
- •14.4 TAP Block Diagram
- •14.5 JTAG Port Architecture
- •14.6 JTAG Bypass Register (JTAGBR)
- •14.7 JTAG Boundary Scan Register (BSR)
- •14.8 TAP Controller
- •14.9 56852 Restrictions
- •B.1 Introduction
- •B.2 Programmer’s Sheets
Resets
10.12 Resets
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the following will occur:
•The SPTE flag is set.
•Any slave mode transmission currently in progress is aborted.
•Any master mode transmission currently in progress is continued to completion.
•The SPI state counter is cleared, making it ready for a new complete transmission.
•All the SPI port logic is disabled.
The following items are reset only by a system reset:
•The SPDTR and SPDRR Registers
•All control bits in the SPSCR Register (MODFEN, ERRIE, SPR1, and SPR0)
•The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, it is possible to clear SPE between transmissions without having to set all control bits again when SPE is set back high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, it is possible to service the interrupts after the SPI has been disabled. Disable SPI by writing 0 to the SPE bit. SPI can also be disabled by a Mode Fault occurring in a SPI configured as a master with MODF.
10.13 Interrupts
Four SPI status flags can be enabled to generate interrupt requests.
Table 10-6. SPI Interrupts
Flag |
Request |
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SPTE (Transmitter Empty) |
SPI Transmitter Interrupt Request (SPTIE = 1,SPE = 1) |
|
SPRF (Receiver Full) |
SPI Receiver Interrupt Request (SPRIE = 1) |
|
|
|
|
OVRF (Overflow) |
SPI Receiver/Error Interrupt Request (ERRIE = 1) |
|
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|
|
MODF (Mode Fault) |
SPI Receiver/Error Interrupt Request (ERRIE = 1) |
|
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|
The following sources in the SPI Status and Control Register can generate interrupt requests:
•The SPI Transmitter Interrupt Enable (SPTIE) bit enables the SPTE flag to generate transmitter interrupt requests provided the SPI is enabled (SPE = 1). The clearing mechanism for the SPTE flag is always just a write to the transmit data register.
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Interrupts
•The SPI Receiver Interrupt Enable (SPRIE) bit enables the SPRF bit to generate receiver interrupt requests regardless of the state of the SPE bit. The clearing mechanism for the SPRF flag is always just a read to the Receive Data Register.
•The Error Interrupt Enable (ERRIE) bit enables both the MODF and OVRF bits to generate a receiver/error controller interrupt request.
•The Mode Fault Enable (MODFEN) bit can prevent the MODF flag from being set so only the OVRF bit is enabled by the ERRIE bit to generate receiver/error controller interrupt requests.
SPTE |
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SPI Transmitter |
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SPTIE |
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Interrupt Request |
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SPE |
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SPRIE
SPRF 
SPI Receiver/Error
Interrupt Request
ERRIE
MODF
OVRF
Figure 10-17. SPI Interrupt Request Generation
The following sources in the SPI Status and Control Register can generate interrupt requests:
•SPI Receiver Full (SPRF) — The SPRF bit becomes set every time a full data transmission transfers from the Shift Register to the Receive Data Register. If the SPI Receiver Interrupt Enable (SPRIE) bit is also set, SPRF can generate a SPI receiver/error interrupt request.
•SPI Transmitter Empty (SPTE) — The SPTE bit becomes set every time a full data transmission transfers from the Transmit Data Register to the Shift Register. If the SPI Transmit Interrupt Enable (SPTIE) bit is also set, SPTE can generate a SPTE interrupt request.
|
Serial Peripheral Interface (SPI), Rev. 4 |
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Interrupts
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
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prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
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Because |
available |
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56852 Digital Signal Controller User Manual, Rev. 4 |
10-30 |
Freescale Semiconductor |
Chapter 11
Improved Synchronous Serial Interface
(ISSI)
|
Improved Synchronous Serial Interface (ISSI), Rev. 4 |
Freescale Semiconductor |
11-1 |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
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of an from |
|
Because |
available |
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-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
|
||
|
Commission, BGA |
prior to September |
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order from the United States International Trade Freescale for import or sale in the United States |
|
|
of an from |
|
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Because |
available |
|
56852 Digital Signal Controller User Manual, Rev. 4 |
11-2 |
Freescale Semiconductor |