56852 Architectural Overview

•Crystal oscillator uses an 2-4MHz crystal

•Ceramic resonator can be used in place of the crystal

•Oscillator output can be divided down by a programmable prescaler

1.2.13.3 PLL

Features of the PLL core provides:

•The PLL generates an interrupt to instruct the controller to gracefully shut down the system in the event the crystal is damaged or destroyed.

•The PLL continues to run for at least 100 instruction cycles if the oscillator source is removed.

•The PLL generates output frequencies up to 240MHz.

•The PLL can be bypassed to use oscillator or prescalar outputs directly.

1.2.13.4 Clock Control

A clock gear shifter guarantees smooth transition from one clock source to the next during normal operation. Clock sources available for normal operation include:

•Crystal oscillator output

•PLL output

•Programmable PLL postscaler output, a divided down version of the PLL output clock; legal divisors are 1, 2, 4, 8, 16, 32, 64, or 128.

1.356852 Architectural Overview

The 56852 consists of the 56800E core, program and data memory, and peripherals useful for embedded control applications. A block diagram of the 56852 is shown in Figure 1-3.

System Bus Controller

Figure 1-3. 56852 Functional Block Diagram

1.4 System Bus Controller

The 56852 System Bus Controller (SBC) provides an interface between the 56800E core and other modules on the system bus. The SBC is composed of a set of buffers for the address and

56852 Overview, Rev. 4

System Bus Controller

control signals originating at the core, and a separate set of multiplexers, routing data from each memory-mapped block back to the core.

The 56852 architecture includes two separate bus models:

1.System bus

2.IPBus

Internal memories and the core are located on the system buses. All peripherals and the external memory interface connect to the IPBus. Access to the IPBus by the core is facilitated by the IPBus bridge. The system bus controller does not participate in IPBus transactions. Within this document, all descriptions of bus operations pertain only to the system bus.

For performance reasons, all system bus signals in the 56852 architecture have a single driver, as opposed to the more common three-state bus configurations. Read data from each memory-mapped device is multiplexed to avoid contention. Since the core is the only system bus master, there is no need for multiplexers on the address, control or write data buses.

1.4.1 Operation Method

The 56800E system utilizes a pipelined memory architecture and separate program and X data buses. Each memory cycle is completed in three or more system clock cycles. During the first of these cycles, the core presents an address, along with control signals, to indicate the type of memory cycle being initiated. This clock cycle is referred to as the address phase of a memory cycle. The following cycle is an intermediate step not involving bus activity related to the memory cycle in progress. Finally, the data phase occurs. During this phase data is transferred to or from the master, depending upon the type of cycle initiated during the address phase.

Memory cycles can overlap in each clock cycle, a new address phase can begin while the data phase for a preceding memory cycle occurs. In certain cases, memory devices or the core may require additional time to complete operations. When this occurs, clock edges to other modules are withheld by the clock generation circuitry. This activity is transparent to the operation of the SBC.

1.4.2 IPBus Bridge (IPBB)

The IPBus Bridge (IPPB) provides a means for communication between the high speed core and the low-bandwidth devices on the IP peripheral bus. Among other functions, the bridge is

System Bus Controller

responsible for maintaining an orderly and synchronized communication between devices on both sides running at two different clock frequencies.

The IPBus architecture supports a variety of on-chip peripherals. Among those peripherals available are:

•Phase-Locked Loop (PLL) module

•16-bit Quad Timer (TMR) module

•Computer Operating Properly (COP) module

•Improved Synchronous Serial Interface (ISSI) module

•Serial Peripheral Interface (SPI) module

•Serial Communication Interface (SCI/UART) module

•Programmable General-Purpose I/O (GPIO) module

Figure 1-1 denotes the position and interface of the IPBus Bridge with other main blocks within the chip.

Other connections in the figure not pertaining to the primary function of the bridge are omitted for clarity; nevertheless, they will be discussed as appropriate. A brief description of bridge’s interface with various main components on both sides is also provided.

1.4.2.1 System Side Operation

On the system side, the IPBus Bridge operates at core frequency and fully supports pipelined communication with the core. The bridge acts as a slave device on this bus. The bridge is responsible for initiating IPBus transactions only per requests initiated by the core, or other system bus masters.

System Bus Controller

CS A D

4 21 16

Figure 1-1. IPBus Bridge Interface With Other Main Components

System Side Operation

1.4.2.2 Peripheral Side Operation

On the peripheral side, the IPBus Bridge accesses various devices through a standard non-pipelined IPBus interface. Separate bus lines are used for read and write transactions. The IPBus Bridge also interfaces with an External Memory Interface (EMI) block. The IPBus operates at half of the core frequency.

56852 Digital Signal Controller User Manual, Rev. 4