Transmission Formats

10.6.3 Wired OR Mode

Wired-OR functionality is provided to permit the connection of multiple SPIs. Figure 10-4 illustrates a single master controlling multiple slave SPIs. When the WOM bit is set, the outputs switch from conventional complementary CMOS output to open drain outputs. This lets the internal pull-up resistor bring the line high, and whichever SPI drives the line pulls it low as needed.

Figure 10-4. Sharing of a Slave by Multiple Masters

10.7 Transmission Formats

During an SPI transmission, data is simultaneously transmitted, or shifted out serially, and received, that is shifted in serially. A serial clock synchronizes shifting and sampling on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices not selected do not interfere with SPI bus activities. On a master SPI device, the Slave Select line can optionally be used to indicate multiple-master bus contention.

Serial Peripheral Interface (SPI), Rev. 4

Transmission Formats

10.7.1 Data Transmission Length

The SPI can support data lengths from one to 16 bits. This can be configured in the Data Size Register (SPDSR). When the data length is less than 16 bits, the Receive Data register will pad the upper bits with zeros. It is the responsibility of the software to remove these upper bits since 16 bits will be read when reading the Receive Data Register (SPDRR).

Note: Data can be lost if the data length is not the same for both master and slave devices.

10.7.2 Data Shift Ordering

The SPI can be configured to transmit or receive the MSB of the desired data first or last. This is controlled by the Data Shift Order (DSO) bit in the SPSCR. Regardless which bit is transmitted or received first, the data shall always be written to the SPI Data Transmit Register (SPDTR) and read from the Receive Data Register (SPDRR) with the LSB in bit 0 and the MSB in the correct position, depending on the data transmission size.

10.7.3 Clock Phase and Polarity Controls

Software can select any of four combinations of Serial Clock (SCLK) phase and polarity using two bits in the SPI Status and Control Register (SPSCR). The Clock Polarity is specified by the (CPOL) control bit. In turn, it selects an active high or low clock and has no significant effect on the transmission format.

The Clock Phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.

Note: Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI Enable (SPE) bit.

10.7.4 Transmission Format When CPHA = 0

Figure 10-5 exhibits an SPI transmission with CPHA as Logic 0. The figure should not be used as a replacement for data sheet parametric information. Two waveforms for the SCLK:

1.CPOL = 0

2.CPOL = 1

The diagram may be interpreted as a master or slave timing diagram since the Serial Clock (SCLK), Master In/Slave Out (MISO), and Master Out/Slave In (MOSI) pins are directly

Transmission Formats

connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master.

The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at Logic 0, because only the selected slave drives to the master. The SS pin of the master is not shown, but it is assumed to be inactive. The SS pin of the master must be high or a mode fault error will occur. When CPHA = 0, the first SCLK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first SCLK edge and a falling edge on the SS pin is used to start the slave data transmission. The slave’s SS pin must be toggled back to high and then low again between each full length data transmitted as depicted in

Figure 10-6.

SS (TO SLAVE)

CAPTURE STROBE

Figure 10-5. Transmission Format (CPHA = 0)

MASTER SS

SLAVE SS (CPHA = 0)

SLAVE SS (CPHA = 1)

Figure 10-6. CPHA/SS Timing

When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the first bit of its data. Once the transmission begins, no new data is allowed into the Shift Register from the Transmit Data Register. Therefore, the SPI Data Register of the slave must be loaded with

Transmission Formats

transmit data before the falling edge of SS. Any data written after the falling edge is stored in the Transmit Data Register and transferred to the Shift Register after the current transmission.

When CPHA = 0 for a master, normal operation would begin by the master initializing the SS pin of the slave high. A transfer would then begin by the master setting the SS pin of the slave low and then writing the SPDTR register. After completion of a data transfer, the SS pin would be put back into the high state by the master device.

10.7.5 Transmission Format When CPHA = 1

A SPI transmission is shown in Figure 10-7 where CPHA is Logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SCLK: 1 for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SCLK), Master In/Slave Out (MISO), and Master Out/Slave In (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at Logic 0, so only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or a mode fault error will occur. When CPHA = 1, the master begins driving its MOSI pin on the first SCLK edge. Therefore, the slave uses the first SCLK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and slave driving the MISO data line.

SS (TO SLAVE)

CAPTURE STROBE

Figure 10-7. Transmission Format (CPHA = 1)

Transmission Formats

When CPHA = 1 for a slave, the first edge of the SCLK indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the first bit of its data. Once the transmission begins, no new data is allowed into the Shift Register from the Transmit Data Register. Therefore, the SPI Data Register of the slave must be loaded with transmit data before the first edge of SCLK. Any data written after the first edge is stored in the Transmit Data Register and transferred to the Shift Register after the current transmission.

10.7.6 Transmission Initiation Latency

When the SPI is configured as a master (SPMSTR = 1), writing to the SPDTR starts a transmission. CPHA has no effect on the delay to the start of the transmission, but it does affect the initial state of the SCLK signal. When CPHA = 0, the SCLK signal remains inactive for the first half of the first SCLK cycle. When CPHA = 1, the first SCLK cycle begins with an edge on the SCLK line from its inactive to its active level. The SPI clock rate, selected by SPR1:SPR0, affects the delay from the write to SPDTR and the start of the SPI transmission. The internal SPI clock in the master is a free-running derivative of the internal clock. To conserve power, it is enabled only when both the SPE and SPMSTR bits are set. Since the SPI clock is free-running, it is uncertain where the write to the SPDTR occurs relative to the slower SCLK. This uncertainty causes the variation in the initiation delay, demonstrated in Figure 10-8. This delay is no longer than a single SPI bit time. That is, the maximum delay is two bus cycles for DIV2, four bus cycles for DIV4, eight bus cycles for DIV8, and so on up to a maximum of 128 cycles for DIV128.